Display apparatus with continuous semiconductor layer
A capacitance setting line is disposed at the top end of a pixel, a light emission setting line is disposed at the bottom end of the pixel, and a gate line is disposed at the center between both the lines. A selection transistor, a potential control transistor and a capacitor are disposed between the gate line and a capacitance setting line. A short-circuit transistor, a drive transistor and a drive control transistor are disposed between the gate line and the light emission setting line. With such an arrangement, the efficient arrangement of wiring contacts can be performed, and an aperture ratio can be increased.
1. A display apparatus including pixels arranged in a matrix, wherein each pixel includes:
a first transistor having one end connected with a data line, the first transistor being turned on and off by a selection signal from a gate line to control reception of a data signal from the data line;
a second transistor which is connected in series between a power source line and a light emitting device, the second transistor, when a voltage in accordance with the data signal received through the first transistor is applied thereto, causing a current from the power source line to flow through the light emitting device in accordance with the data signal;
a third transistor which is turned on and off by application of the selection signal to a gate electrode of the third transistor from the gate line and is connected between a gate electrode of the second transistor and one end of the second transistor; and
a fourth transistor which is connected in series between the power source line and the light emitting device, the fourth transistor being turned on and off by application of a signal to a gate electrode of the fourth transistor from a line which is provided as a common line for a row of pixels,
wherein the third transistor and the fourth transistor are formed with a single continuous semiconductor layer which is provided to be opposed to the gate electrode of the third transistor and the gate electrode of the fourth transistor with an insulation film interposed therebetween, and
the third transistor and the fourth transistor are connected with each other through the semiconductor layer.
2. The display apparatus according to claim 1 , wherein
the semiconductor layer that connects the third transistor and the fourth transistor is formed along the power source line or the data line within a display plane.
3. The display apparatus according to claim 1 wherein
the semiconductor layer forming a channel region of the third transistor or the fourth transistor is formed so as to extend in parallel with the gate line.
4. The display apparatus according to claim 3 wherein
the semiconductor layer forming a channel region of the third transistor and the fourth transistor is formed so as to extend in parallel with the gate line.
5. The display apparatus according to claim 1 , wherein
the gate of the second transistor is connected with a capacitor.
6. The display apparatus according to claim 5 , wherein
the capacitor includes a layer which is in the same layer as that of a semiconductor layer forming the second transistor and a layer which is in the same layer as that of a gate electrode of the second transistor, that are opposite each other.
7. The display apparatus according to claim 5 , wherein
the capacitor is partially superposed on the power source line.
8. The display apparatus according to claim 1 , wherein
said one end of the second transistor to which the third transistor is connected is a drain of the second transistor.