Providing a ready-busy signal from a non-volatile memory device to a memory controller
View Patent ↗A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to.
1. A non-volatile memory, comprising:
a calibration pin configured to provide a signal for calibrating a drive strength of the non-volatile memory when the non-volatile memory is in a first state and to provide a ready/busy signal indicative of whether the non-volatile memory is ready to write when the non-volatile memory is in a second state.
2. The non-volatile memory of claim 1 , wherein the calibration pin is an output pin, a ZQ pin, or a combination thereof.
3. The non-volatile memory of claim 1 , wherein the calibration pin is configured to provide the ready/busy signal using a current source.
4. The non-volatile memory of claim 3 , further comprising:
a control configured to selectively couple the current source to the calibration pin.
5. The non-volatile memory of claim 1 , wherein the non-volatile memory is configured to be in the first state when executing a read command and configured to be in the second state when executing a write command.
6. The non-volatile memory of claim 1 , wherein the calibration pin is coupled to a resistor.
7. A method, comprising:
providing a ready signal on a calibration pin of a non-volatile memory responsive, at least in part, to the non-volatile memory having a ready state; and
receiving a write command responsive, at least in part, to said providing the ready signal.
8. The method of claim 7 , further comprising:
before said providing a ready signal, providing a wait signal on the calibration pin responsive, at least in part, to the non-volatile memory having a busy state.
9. The method of claim 8 , wherein the non-volatile memory is configured to have the busy state when executing a write command.
10. The method of claim 7 , wherein said receiving a write command comprises:
receiving the write command from a memory controller.
11. The method of claim 7 , wherein the calibration pin is at least one of an output pin, a ZQ pin, or a combination thereof.
12. The method of claim 7 , wherein said providing a ready signal comprises:
selectively coupling a current source to the calibration pin using a control.
13. The method of claim 7 , further comprising:
executing the write command; and
calibrating a drive strength in accordance with a signal provided by the calibration pin.
14. A method, comprising:
calibrating a drive strength based, at least in part, on a signal provided by a pin responsive, at least in part, to the non-volatile memory having a first state; and
providing a ready signal on the pin indicating the non-volatile memory is ready to write responsive, at least in part, to the non-volatile memory having a second state.
15. The method of claim 14 , further comprising:
providing a busy signal indicating that the non-volatile memory is busy responsive, at least in part, to the non-volatile memory executing a memory command while in the second state.
16. The method of claim 14 , wherein said providing a ready signal comprises:
selectively coupling a current source to the pin based, at least in part, on a control signal.
17. The method of claim 14 , wherein said calibrating a drive strength with a pin, comprises:
calibrating the drive strength with the pin for communication with a memory controller.
18. The method of claim 14 , wherein the non-volatile memory is a phase change memory (PCM).
19. The method of claim 14 , wherein the non-volatile memory is configured to be in the first state when executing a read command and configured to be in the second state when executing a write command.