Eco logic cell and design change method using eco logic cell
The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.
1. A logic cell within an integrated circuit comprising buffer cells and logic cells, comprising:
a buffer cell input node configured to receive an input signal;
a buffer cell output node configured to output a result of a logic operation on the input signal;
a buffer cell active layer;
a buffer cell polysilicon layer; and
a reconfigured buffer cell metal layer connecting the buffer cell polysilicon layer to the buffer cell active layer, or to the buffer cell input node, or to the buffer cell output node, wherein a buffer cell from among the buffer cells is transformed into the logic cell other than another buffer cell from among the buffer cells by the reconfigured buffer cell metal layer.
2. The logic cell of claim 1 , wherein the buffer cell active layer includes drain and source regions of a transistor.
3. The logic cell of claim 2 , wherein the buffer cell polysilicon layer includes a gate region of the transistor.
4. The logic cell of claim 3 , wherein the buffer cell active layer of the logic cell is narrower in area than an active layer of a non-reconfigured logic cell, from among the logic cells, within the integrated circuit.
5. The logic cell of claim 3 , wherein the buffer cell active layer of the logic cell is wider in area than an active layer of a non-reconfigured inverter cell, from among the logic cells, within the integrated circuit.
6. The logic cell of claim 3 , wherein the buffer cell input node is connected to a transistor having a relatively low drive capacity from among a plurality of transistors included in the logic cell.
7. The logic cell of claim 6 , wherein the buffer cell output node is connected to a transistor having a relatively strong drive capacity from among the plurality of transistors included in the logic cell.