Multi-port memory devices and methods having programmable impedance elements
View Patent ↗A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports.
1. A memory device, comprising:
at least two ports for transferring data to and from the memory device; and
plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of N access devices, each access device providing a current path between the element and a different one of the ports; wherein N is at least two;
each element is a two terminal element that changes from one impedance state to another when a current greater than a program current flows through it; and
each access device is configured to limit a current through it to less than 1/N of the program current in a read operation.
2. The memory device of claim 1 , wherein:
the memory elements comprise a programmable resistance material formed between two electrodes.
3. The memory device of claim 2 , wherein:
the memory elements each comprise a solid state electrolyte in which conductive regions are formed and dissolved.
4. The memory device of claim 1 , wherein:
each access device comprises an insulated gate field effect transistor.
5. The memory device of claim 1 , wherein:
each memory cell includes
two elements programmable to different impedance states, and
the access devices include a pair of access devices corresponding to each port, one access device of each pair coupling one element to its port, the other access device of the pair coupling the other element to its port.
6. The memory device of claim 1 , wherein:
the memory cells are arranged into an array of rows and columns, memory cells of a same row having access devices connected to same group of word lines, and memory cells of a same column having access devices connected to same group of bit lines.
7. The memory device of claim 1 , wherein:
a control circuit configured to enable multiple access devices of a memory cell at the same time in response to simultaneous read accesses from the ports corresponding to such access devices.
8. The memory device of claim 1 , wherein:
the access devices are configured to provide simultaneous current paths between corresponding ports and the element in response to simultaneous read operations at the ports.
9. The memory device of claim 1 , wherein:
the access devices are configured to provide one current path between one port and the corresponding element in response to simultaneous accesses at multiple ports, one of which is a write access.
10. A memory device, comprising:
a plurality of memory elements, each programmable between at least two different impedance states; and
a set of N access devices corresponding to each memory element, each configured to enable and disable a current path to a different access port in response to different selection signals; wherein
N is at least two;
each memory element is a two terminal element that changes from one impedance state to another when a current greater than a program current flows through it; and
each access device is configured to limit a current through it to less than 1/N of the program current in a read operation.
11. The memory device of claim 10 , wherein:
each set of N access devices is configured to enable only one of the access devices in response to one of multiple accesses being a write access.
12. The memory device of claim 10 , wherein:
the access devices are enabled and disabled according to a periodic timing signal for synchronous accesses to the memory elements.
13. The memory device of claim 10 , wherein:
the access devices are enabled and disabled according to input signals for asynchronous accesses to the memory elements.
14. The memory device of claim 10 , wherein:
each set of N access devices is configured to enable only one of the access devices in response to write accesses from multiple ports to the corresponding memory element.
15. A method, comprising:
in a memory device having a plurality of memory elements programmable between at least two different impedance states,
enabling current paths between a memory element and multiple ports in response to read requests on the multiple ports at the same time,
in a read operation,
applying a read bias voltage to one terminal of a memory element, and
preventing a flow of current through the memory element to less than a disturb current regardless of how many current paths are enabled; wherein
a disturb current can alter an impedance of the memory element by more than a predetermined amount.
16. The method of claim 15 , further including:
enabling only one current path to one port, in response to a write request on one port and another access request on another port at the same time.
17. The method of claim 15 , further including:
in a read operation,
detecting a current flow through the memory element; wherein
the memory element has an impedance that varies according to conductive regions that formed and dissolved according to an applied electric field.
18. The method of claim 15 , further including:
in response to a write request at one port,
enabling a first write current to flow through the memory element in a first direction via only one of the current paths in response to first write data, and
enabling a second write current to flow through the memory element in a second direction via only one of the current paths in response to second write data.