Airgap structure and method of manufacturing thereof
A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.
1. A method of fabricating a gate structure comprising:
providing a gate structure assembly having a plurality of gates disposed across a substrate defined by a network of spaces, the gate structure assembly defined by a dense word line (WL) region;
applying a deposition layer to form void spaces in any space of the dense WL region;
forming a first interlayer dielectric across the gate structure;
removing a cap layer disposed on the gate structure to form openings in the void spaces;
constructing a silicide layer on the plurality of gates; and
forming a second interlayer dielectric across the plurality of gates, wherein the second interlayer dielectric comprises a buffer oxide layer, silicon nitride film, and at least one of a silicon oxide layer and an undoped silicon glass layer.
2. The method of claim 1 , additionally comprising:
applying a fill material to fill the void spaces;
removing any excess fill material from the gate structure; and
forming an oxide recess over the network of spaces.
3. The method of claim 2 , additionally comprising removing the fill material from the void spaces to form a plurality of airgaps.
4. The method of claim 2 , wherein the fill material is a spin-on dielectric material.
5. The method of claim 4 , wherein applying a fill material to fill the void spaces comprises:
spinning on the spin-on dielectric material;
baking the spin-on dielectric material using a soft bake process; and
curing the spin-on dielectric material.
6. The method of claim 1 , wherein the deposition layer is applied using a chemical vapor deposition (CVD) process.
7. The method of claim 1 , wherein the silicide comprises cobalt.
8. The method of claim 7 , wherein constructing a silicide layer on the plurality of gates comprises:
applying a layer of cobalt across the gate structure;
heating the control gate using a first rapid thermal process;
removing unreacted cobalt from the gate structure; and
heating the control gate using a second rapid thermal process.
9. The method of claim 8 , wherein the first rapid thermal process operates at a temperature in a range of from about 400° C. to about 680° C. for an amount of time in a range of from about 10 seconds to about 40 seconds.
10. The method of claim 8 , wherein the second rapid thermal process operates at a temperature in a range of from about 700° C. to about 950° C. for an amount of time in a range of from about 30 seconds to about 60 seconds.
11. A method of fabricating a gate structure comprising:
providing a gate structure assembly having a plurality of gates disposed across a substrate defined by a network of spaces, the gate structure assembly defined by a dense word line (WL) region;
applying a deposition layer to form void spaces in any space of the dense WL region;
forming a first interlayer dielectric across the gate structure;
removing a cap layer disposed on the gate structure to form openings in the void spaces;
applying a fill material to fill the void spaces;
constructing a silicide layer on the plurality of gates;
removing the fill material from the void spaces to form a plurality of airgaps; and
forming a second interlayer dielectric across the airgaps, wherein the second interlayer dielectric comprises a buffer oxide layer, silicon nitride film, and at least one of a silicon oxide layer and an undoped silicon glass layer, and
wherein the airgaps extend into the second interlayer dielectric.