IP Library Granted Patent US 8,901,909
Granted Patent B2
US 8,901,909 · App. 13/618,617 · Granted Dec 2, 2014

Multi-phase power system with redundancy

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Quick Facts
Patent No.
US 8,901,909
App. No.
13/618,617
Granted
Dec 2, 2014
Kind
B2
Abstract

An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Claims (39)

1. A system for delivering power to a load, the system comprising:

a first power module comprising circuitry configured to generate a first plurality of control signals, the first power module being configured to deliver a first amount of current to the load in response to a first one of the first plurality of control signals; and

a second power module comprising circuitry configured to generate a second plurality of control signals, the second power module being configured to deliver a second amount of current to the load in response to a second one of the first plurality of control signals;

wherein the first power module is further configured to detect a fault condition based on a comparison of the first amount of current and the second amount of current, and wherein the first amount of current or the second amount is adjusted upon detection of the fault condition.

2. The system of claim 1 , wherein the second power module is configured to receive the second one of the first plurality of control signals from the first power module via a first bus.

3. The system of claim 1 , further comprising:

a third power module comprising circuitry configured to generate a third plurality of control signals, the third power module being configured to deliver a third amount of current to the load in response to a third one of the first plurality of control signals;

wherein the first power module is configured to sequentially deliver the second one of the first plurality of control signals and the third one of the first plurality of control signals to the second power module and the third power module, respectively.

4. The system of claim 1 , wherein:

the first amount of current depends on a duty cycle represented on the first one of the first plurality of control signals, and

the second amount of current depends on a duty cycle represented on the second one of the first plurality of control signals.

5. The system of claim 1 , wherein the first plurality of control signals include digital pulse-width modulated (DPWM) control signals.

6. The system of claim 1 , wherein at least one of the first amount of current or the second amount of current is capable of being changed based on the second plurality of control signals when the fault condition is detected in the first power module.

7. The system of claim 5 , wherein at least one of the DPWM control signals include a digitally-encoded representation of a corresponding analog PWM signal having a duty cycle determined by the digitally-encoded representation.

8. The system of claim 1 , wherein the first amount of current is substantially equal to the second amount of current when the fault condition is not detected.

9. The system of claim 1 , wherein the first plurality of control signals includes pulse-width modulated (PWM) control signals.

10. The system of claim 1 , wherein each of the first power module and the second power module is configured to operate in accordance with a single clock signal.

11. The system of claim 1 , wherein each of the first power module and the second power module is configured to operate at a same frequency and at a same phase.

12. The system of claim 1 , wherein each of the first power module and the second power module is configured to operate at a same frequency and at different phases.

13. A method of operation within an integrated circuit device, the method comprising:

generating a first plurality of control signals in a first power circuit;

delivering, by the first power circuit, a first amount of current to a load in response to a first one of the first plurality of control signals;

delivering, by a second power circuit, a second amount of current to the load in response to a second one of the first plurality of control signals; and

dynamically configuring at least one of the first amount of current or the second amount of current being delivered to the load; including,

detecting a fault condition based on a comparison of at least the first amount of current and the second amount of current; and

adjusting the first amount of current or the second amount of current upon detection of the fault condition.

14. The method of claim 13 , wherein the first amount of current is substantially equal to the second amount of current when the fault condition is not detected.

15. The method of claim 13 , further comprising:

delivering, by a third power circuit, a third amount of current to the load in response to a third one of the first plurality of control signals; and

generating a second plurality of control signals in the second power circuit, wherein the dynamically configuring includes dynamically configuring at least one of the first amount of current, the second amount of current, or the third amount of current based on the second plurality of control signals when the fault condition is detected in the first power circuit.

16. The method of claim 13 , wherein the first plurality of control signals includes pulse-width modulated (PWM) control signals.

17. The method of claim 13 , wherein the first plurality of control signals includes digital pulse-width modulated (DPWM) control signals.

18. The method of claim 17 , wherein at least one of the DPWM control signals include a digitally-encoded representation of a corresponding analog PWM signal having a duty cycle determined by the digitally-encoded representation.

19. A system for delivering power to a load, the system comprising:

a first power module comprising circuitry configured to generate a first plurality of control signals, the first power module being configured to deliver a first amount of current to the load in response to a first one of the first plurality of control signals;

a second power module comprising circuitry configured to deliver a second amount of current to the load in response to a second one of the first plurality of control signals; and

a third power module comprising circuitry configured to deliver a third amount of current to the load in response to a third one of the first plurality of control signals;

wherein the first power module is further configured to detect a fault condition based on a comparison of the first amount of current, the second amount of current, and the third amount of current.

20. The system of claim 19 , wherein one of the first amount of current, the second amount of current, or the third amount of current is adjusted upon determination of the fault condition.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2014
From: KHANNA, SANDEEP; SRINIVASAN, MAHESHWARAN; LI, DE CAI; DESHPANDE, CHETAN
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 034024/0740 →