Resistive memory and methods of processing resistive memory
View Patent ↗Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.
1. A resistive memory cell, comprising:
a bottom electrode directly connected to an access device;
a resistive memory cell material on the bottom electrode;
a top electrode on the resistive memory cell material, wherein;
the top electrode is a heater electrode; and
the top electrode is self-aligned to the resistive memory cell material;
a metal spacer on the resistive memory cell material and adjacent a sidewall of the top electrode; and
a dielectric spacer on the resistive memory cell material and adjacent a sidewall of the metal spacer.
2. The resistive memory cell of claim 1 , wherein a width of the top electrode is smaller than a width of the bottom electrode.
3. The resistive memory cell of claim 1 , wherein the top electrode has a width of approximately 100 Angstroms.
4. The resistive memory cell of claim 1 , wherein the top electrode includes titanium nitride.
5. The resistive memory cell of claim 1 , wherein the top electrode includes tungsten.
6. The resistive memory cell of claim 1 , wherein the top electrode is not directly connected to the access device.
7. A memory device, comprising:
an array of memory cells, wherein a number of the memory cells include:
an electrode directly connected to an access device;
a phase change random access memory (PCRAM) cell material on the electrode;
a heater electrode on the PCRAM cell material, wherein the heater electrode is self-aligned to the PCRAM cell material;
a metal spacer on the PCRAM cell material and adjacent a sidewall of the heater electrode; and
a dielectric spacer on the PCRAM cell material and adjacent a sidewall of the metal spacer.
8. The memory device of claim 7 , wherein a first number of memory cells in the array are stacked on a second number of memory cells in the array.
9. The memory device of claim 8 , wherein the first number of memory cells and second number of memory cells are coupled to a common data line.