Multiplexing physical neurons to optimize power and area

1. A neural core circuit, comprising:

a memory device that maintains neuronal attributes for multiple neurons, wherein the memory device has multiple entries, and each entry maintains neuronal attributes for a corresponding neuron; and

a controller that manages the memory device and processes neuronal firing events targeting each neuron;

wherein the controller multiplexes computation and control logic for said neurons; and

wherein, in response to neuronal firing events targeting one of said neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates said firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.

2. The neural core circuit of claim 1 , wherein:

for each of said entries, the neuronal attributes maintained in said entry include synaptic connectivity information, neuron parameters, and routing data information for a corresponding neuron.

3. The neural core circuit of claim 2 , wherein:

the controller generates said firing event for said target neuron if integrated firing events exceed a threshold neuron parameter for said target neuron.

4. The neural core circuit of claim 3 , wherein:

for each target neuron, the controller updates at least one neuron parameter for said target neuron.

5. The neural core circuit of claim 2 , wherein:

for each neuron that corresponds to an entry of the memory device, the controller:

receives incoming firing events targeting said neuron; and

retrieves synaptic connectivity information for said neuron from the corresponding entry of the memory device.

6. The neural core circuit of claim 5 , wherein:

for each neuron that corresponds to an entry of the memory device, the controller:

retrieves neuron parameters for said neuron from the corresponding entry of the memory device;

integrates incoming firing events targeting said neuron, wherein the incoming firing events are integrated based on the neuron parameters and synaptic connectivity information for said neuron;

generates an outgoing firing event when the integrated incoming firing events exceed a threshold neuron parameter for said neuron, wherein the outgoing firing event is generated based on the routing data information for said neuron; and

updates at least one neuron parameter for said neuron.

7. The neural core circuit of claim 1 , wherein:

for each time step, each entry of the memory device is read out sequentially.

8. The neural core circuit of claim 1 , wherein:

the memory device is a memory array including multiple partitions; and

said multiple partitions include:

a first partition maintaining synaptic connectivity information for said multiple neurons;

a second partition maintaining neuron parameters for said multiple neurons; and

a third partition maintaining routing data information for said multiple neurons.

9. The neural core circuit of claim 1 , wherein:

the memory device includes multiple memory arrays; and

said multiple memory arrays include:

a first memory array maintaining synaptic connectivity information for said multiple neurons;

a second memory array maintaining neuron parameters for said multiple neurons; and

a third memory array maintaining routing data information for said multiple neurons.

10. A method, comprising:

maintaining neuronal attributes for multiple neurons in a memory device, wherein the memory device has multiple entries, and each entry maintains neuronal attributes for a corresponding neuron; and

utilizing a controller to manage the memory device and process neuronal firing events targeting each neuron;

wherein the controller multiplexes computation and control logic for said neurons; and

wherein, in response to neuronal firing events targeting one of said neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates said firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.

11. The method of claim 10 , further comprising:

for each of said entries, maintaining synaptic connectivity information, neuron parameters, and routing data information for a corresponding neuron in said entry.

12. The method of claim 11 , further comprising:

generating said firing event for said target neuron if integrated firing events exceed a threshold neuron parameter for said target neuron.

13. The method of claim 12 , further comprising:

for each target neuron, updating at least one neuron parameter for said target neuron.

14. The method of claim 11 , further comprising:

for each neuron that corresponds to an entry of the memory device:

receiving incoming firing events targeting said neuron; and

retrieving synaptic connectivity information for said neuron from the corresponding entry of the memory device.

15. The method of claim 14 , further comprising:

for each neuron that corresponds to an entry of the memory device:

retrieving neuron parameters for said neuron from the corresponding entry of the memory device;

integrating incoming firing events targeting said neuron, wherein the incoming firing events are integrated based on the neuron parameters and synaptic connectivity information for said neuron;

generating an outgoing firing event when the integrated incoming firing events exceed a threshold neuron parameter for said neuron, wherein the outgoing firing event is generated based on the routing data information for said neuron; and

updating at least one neuron parameter for said neuron.

16. The method of claim 10 , further comprising:

for each time step, reading out sequentially each entry of the memory device.

17. The method of claim 10 , further comprising:

maintaining synaptic connectivity information for said multiple neurons in a first partition of a memory array;

maintaining neuron parameters for said multiple neurons in a second partition of the memory array; and

maintaining routing data information for said multiple neurons in a third partition of the memory array.

18. The method of claim 10 , further comprising:

maintaining synaptic connectivity information for said multiple neurons in a first memory array;

maintaining neuron parameters for said multiple neurons in a second memory array; and

maintaining routing data information for said multiple neurons in a third memory array.

19. A non-transitory computer program product for a neural core circuit, the computer program product comprising a non-transitory computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:

maintain neuronal attributes for multiple neurons in a memory device, wherein the memory device has multiple entries, and each entry maintains neuronal attributes for a corresponding neuron; and

utilize a controller to manage the memory device and process neuronal firing events targeting each neuron;

wherein the controller multiplexes computation and control logic for said neurons; and

wherein, in response to neuronal firing events targeting one of said neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates said firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.

20. The program code of claim 19 , further executable by the computer to:

for each of said entries, maintain synaptic connectivity information, neuron parameters, and routing data information for a corresponding neuron in said entry.

21. The program code of claim 20 , further executable by the computer to:

generate said firing event for said target neuron if integrated firing events exceed a threshold neuron parameter for said target neuron.

22. The program code of claim 21 , further executable by the computer to:

for each target neuron, update at least one neuron parameter for said target neuron.

23. The program code of claim 19 ,

wherein, for each time step, each entry of the memory device is read out sequentially.