REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT
A memory interface circuit device comprising a data structure configured to match and substitute an address in a run-time.
1 . A memory interface circuit device comprising:
a data structure configured to match and substitute an address in a run-time.
2 . The interface circuit device of claim 1 is coupled to a DRAM device having a spare memory cell.
3 . The interface circuit device of claim 1 is coupled to a DRAM device having a spare memory cell to be configured as a low latency memory system, the DRAM device being configured to be addressable from the interface circuit.
4 . The interface circuit device of claim 1 is coupled to a host memory controller.
5 . The interface circuit device of claim 1 further comprising a command and address control coupled to a host memory controller.
6 . The interface circuit device of claim 1 wherein the data structure is provided in an address match table coupled to a command and address control.
7 . A low latency DRAM device comprising a spare memory cell, the spare memory cell coupled to an external address.
8 . The DRAM device of claim 7 is coupled to an interface circuit the interface circuit configured to the DRAM device.