IP Library Granted Patent US 9,530,675
Granted Patent B2
US 9,530,675 · App. 13/622,556 · Granted Dec 27, 2016

Wafer handling station including cassette members with lateral wafer confining brackets and associated methods

Inventor: Romolo Recorba Bactasa (Serangoon, SG)
Assignee: STMICROELECTRONICS PTE LTD
H01L21/67309H01L21/67303H05K13/0084Y10T29/49826
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Quick Facts
Patent No.
US 9,530,675
App. No.
13/622,556
Granted
Dec 27, 2016
Kind
B2
Abstract

A wafer handling station includes a housing defining a chamber, and a wafer cassette assembly positionable in the chamber. The wafer cassette assembly includes a vertical support, and cassette members carried by the vertical support in spaced relation. Each cassette member includes a base coupled to the vertical support, wafer contact pads on an upper surface of the base and configured to support a wafer thereon, and a pair of wafer brackets carried by the base and configured to engage respective edges of the wafer to laterally confine the wafer.

Claims (37)

1. A wafer handling station comprising:

a housing defining a chamber; and

a wafer cassette assembly positionable in the chamber and comprising

a vertical support, and

a plurality of cassette members carried by said vertical support in spaced relation and configured to hold a plurality of semiconductor wafers, each cassette member comprising

a substantially planar base coupled to said vertical support, said base having a proximal end coupled to said vertical support and having a pair of distal ends spaced from the proximal end and not coupled to said vertical support,

a plurality of wafer contact pads on an upper surface of said base and configured to support a respective semiconductor wafer thereon, and

a pair of wafer brackets carried by said base and outwardly extending beyond outer edges of said base and configured to engage respective edges of the respective semiconductor wafer to laterally confine the respective semiconductor wafer.

2. The wafer handling station according to claim 1 wherein said plurality of wafer contact pads comprises a proximal wafer contact pad adjacent the proximal end of said base and a pair of distal wafer contact pads adjacent the respective distal ends of said base; and wherein said pair of wafer brackets are adjacent the respective distal ends of said base.

3. The wafer handling station according to claim 2 wherein each wafer bracket is coupled to a respective distal wafer contact pad.

4. The wafer handling station according to claim 3 wherein each wafer bracket and respective distal wafer contact pad are integrally formed as a monolithic unit.

5. The wafer handling station according to claim 1 wherein said base has a central recess therein aligned with the respective semiconductor wafer and a V-shaped notch in communication with the central recess.

6. The wafer handling station according to claim 1 wherein each wafer bracket has an L-shape.

7. The wafer handling station according to claim 1 wherein said pair of wafer brackets is positioned on said base so that the respective wafer is laterally confined at respective locations past a halfway position of the respective wafer.

8. The wafer handling station according to claim 1 wherein said base has a proximal end coupled to said vertical support; and wherein said vertical support comprises a plurality of stacked proximal wafer brackets, with each proximal wafer bracket adjacent the proximal end of a respective base and defining a backstop for the respective semiconductor wafer.

9. A wafer cassette assembly for a wafer handling station comprising:

a vertical support; and

a plurality of cassette members carried by said vertical support in spaced relation and configured to hold a plurality of semiconductor wafers, each cassette member comprising

a substantially planar base coupled to said vertical support, said base having a proximal end coupled to said vertical support and having a pair of distal ends spaced from the proximal end and not coupled to said vertical support,

a plurality of wafer contact pads on an upper surface of said base and configured to support a respective semiconductor wafer thereon, and

a pair of wafer brackets carried by said base and outwardly extending beyond outer edges of said base and configured to engage respective edges of the respective semiconductor wafer to laterally confine the respective semiconductor wafer.

10. The wafer cassette assembly according to claim 9 wherein said plurality of wafer contact pads comprises a proximal wafer contact pad adjacent the proximal end of said base and a pair of distal wafer contact pads adjacent the respective distal ends of said base; and wherein said pair of wafer brackets are adjacent the respective distal ends of said base.

11. The wafer cassette assembly according to claim 10 wherein each wafer bracket is coupled to a respective distal wafer contact pad.

12. The wafer cassette assembly according to claim 11 wherein each wafer bracket and respective distal wafer contact pad are integrally formed as a monolithic unit.

13. The wafer cassette assembly according to claim 9 wherein said base has a central recess therein aligned with the respective semiconductor wafer and a V-shaped notch in communication with the central recess.

14. The wafer cassette assembly according to claim 9 wherein each wafer bracket has an L-shape.

15. The wafer cassette assembly according to claim 9 wherein said pair of wafer brackets is positioned on said base so that the respective semiconductor wafer is laterally confined at respective locations past a halfway position of the respective semiconductor wafer.

16. The wafer cassette assembly according to claim 9 wherein said base has a proximal end coupled to said vertical support; and wherein said vertical support comprises a plurality of stacked proximal wafer brackets, with each proximal wafer bracket adjacent the proximal end of a respective base and defining a backstop for the respective semiconductor wafer.

17. A method for making a cassette member to be coupled to a vertical support for a wafer handling station, comprising

forming a substantially planar base to be coupled to the vertical support, the base having a proximal end to be coupled to the vertical support and having a pair of distal ends spaced from the proximal end and not coupled to the vertical support;

coupling a plurality of wafer contact pads on an upper surface of the base and configured to support a respective wafer thereon; and

coupling a pair of wafer brackets to the base and outwardly extending beyond outer edges of the base and configured to engage respective edges of the respective wafer to laterally confine the respective wafer.

18. The method according to claim 17 wherein the plurality of wafer contact pads comprises a proximal wafer contact pad adjacent the proximal end of the base and a pair of distal wafer contact pads adjacent the respective distal ends of the base; and wherein the pair of wafer brackets are adjacent the respective distal ends of the base.

19. The method according to claim 18 wherein each wafer bracket is coupled to a respective distal wafer contact pad.

20. The method according to claim 19 wherein each wafer bracket and respective distal wafer contact pad are integrally formed as a monolithic unit.

21. The method according to claim 18 wherein each wafer bracket has an L-shape.

22. The method according to claim 18 wherein the pair of wafer brackets is positioned on the base so that the respective wafer is laterally confined at respective locations past a halfway position of the respective wafer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2022
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060127/0427 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2012
From: BACTASA, ROMOLO
To: STMICROELECTRONICS PTE. LTD.
Reel/Frame 029151/0737 →
Continuity (1)
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