Electrical hotspot detection, analysis and correction

1. One or more non-transitory processor-readable storage media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

receiving information of a circuit design and a layout design for an integrated circuit, and information of electrical constraints, the circuit design comprising one or more analog circuits, the electrical constraints being associated with the electrical behavior of one or more analog electrical devices employed by the integrated circuit, analog device instances of the one or more analog electrical devices being linked to corresponding geometric features in the layout design:

extracting layout parameters for the analog device instances;

computing electrical parameter variations for the analog device instances based on the extracted layout parameters to identify one or more electrical hotspots in one or more of the analog device instances in the layout design;

performing sensitivity analysis of the one or more electrical hotspots to generate repair hints, the sensitivity analysis including analysis of the effect of mechanical stress due to at least one of well proximity or shallow trench isolation on the electrical behavior of the one or more analog device instances, the repair hints including one or more diffusion edge modifications of the respective one or more analog device instances associated with the one or more electrical hotspots;

adjusting the layout design based on the repair hints; and

outputting the adjusted layout design.

2. The one or more processor-readable storage media recited in claim 1 , wherein the circuit design comprises a transistor-level netlist.

3. The one or more processor-readable storage media recited in claim 1 , wherein the layout parameters comprise one or more of context-aware stress parameters and lithography-aware dimension parameters.

4. The one or more processor-readable storage media recited in claim 1 , wherein the computing comprises:

using device model equations for deriving values of analog electrical device parameters.

5. The one or more processor-readable storage media recited in claim 4 , wherein the analog electrical device parameters comprise one or more of saturation current, channel mobility, threshold voltage, channel length, channel width, SA parameter, and SB parameter.

6. The one or more processor-readable storage media recited in claim 1 , wherein the computing comprises:

using a simulation-based technique for deriving values of analog electrical device parameters.

7. The one or more processor-readable storage media recited in claim 6 , wherein the using comprises:

extracting a minimized transistor-level netlist from a transistor-level netlist of the circuit design based on information of the analog device instances; and

simulating the minimized transistor-level netlist.

8. The one or more processor-readable storage media recited in claim 6 , wherein the using comprises:

simulating the circuit design.

9. The one or more processor-readable storage media recited in claim 6 , wherein the analog electrical device parameters comprise one or more of saturation current, channel mobility, threshold voltage, channel length, channel width, SA parameter, and SB parameter.

10. The one or more processor-readable storage media recited in claim 1 , wherein the sensitivity analysis further comprises lithography variation effect analysis, layout proximity effect analysis, or any combinations thereof.

11. The one or more processor-readable storage media recited in claim 1 , wherein the adjusting comprises:

using a smart cost-function technique to adjust the layout design.

12. The one or more processor-readable storage media recited in claim 1 , wherein the one or more analog electrical devices comprise one or more analog designs selected from current mirrors, differential pairs, and amplifiers.

13. The method recited in claim 1 , wherein the diffusion edge modifications correspond to a minimum change in saturation current of the one or more analog device instances.

14. A method of electrical hotspot detection and correction, comprising:

with a computer,

receiving information of a circuit design and a layout design for an integrated circuit, and information of electrical constraints, the circuit design comprising one or more analog circuits, the electrical constraints being associated with the electrical behavior of one or more analog electrical devices employed by the integrated circuit, analog device instances of the one or more analog electrical devices being linked to corresponding geometric features in the layout design;

extracting layout parameters for the analog device instances;

computing electrical parameter variations for the analog device instances based on the extracted layout parameters to identify one or more electrical hotspots in one or more of the analog device instances in the layout design;

performing sensitivity analysis of the one or more electrical hotspots to generate repair hints, the sensitivity analysis including analysis of the effect of mechanical stress due to at least one of well proximity or shallow trench isolation on the electrical behavior of the one or more analog device instances, the repair hints including one or more diffusion edge modifications of the respective one or more analog device instances associated with the one or more electrical hotspots;

adjusting the layout design based on the repair hints; and

outputting the adjusted layout design.

15. The method recited in claim 14 , wherein the circuit design comprises a transistor-level netlist.

16. The method recited in claim 14 , wherein the layout parameters comprise one or more of context-aware stress parameters and lithography-aware dimension parameters.

17. The method recited in claim 14 , wherein the computing comprises:

using device model equations for deriving values of analog electrical device parameters.

18. The method recited in claim 17 , wherein the analog electrical device parameters comprise one or more of saturation current, channel mobility, threshold voltage, channel length, channel width, SA parameter, and SB parameter.

19. The method recited in claim 14 , wherein the computing comprises:

using a simulation-based technique for deriving values of analog electrical device parameters.

20. The method recited in claim 19 , wherein the using comprises:

extracting a minimized transistor-level netlist from a transistor-level netlist of the circuit design based on information of the analog device instances; and

simulating the minimized transistor-level netlist.

21. The method recited in claim 19 , wherein the using comprises:

simulating the circuit design.

22. The method recited in claim 19 , wherein the analog electrical device parameters comprise one or more of saturation current, channel mobility, threshold voltage, channel length, channel width, SA parameter, and SB parameter.

23. The method recited in claim 14 , wherein the sensitivity analysis further comprises lithography variation effect analysis, layout proximity effect analysis, or any combinations thereof.

24. The method recited in claim 14 , wherein the adjusting comprises:

using a smart cost-function technique to adjust the layout design.

25. The method recited in claim 14 , wherein the one or more analog electrical devices comprise one or more analog designs selected from current mirrors, differential pairs, and amplifiers.

26. The method recited in claim 14 , wherein the diffusion edge modifications correspond to a minimum change in saturation current of the one or more analog device instances.

27. One or more non-transitory processor-readable storage media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

receiving information of a circuit design and a layout design for an integrated circuit, and information of user-defined electrical constraints, the circuit design comprising one or more analog circuits, the user-defined electrical constraints being associated with the electrical behavior of one or more analog electrical devices employed by the integrated circuit, analog device instances of the one or more analog electrical devices being linked to corresponding geometric features in the layout design;

extracting layout parameters for the analog device instances;

computing electrical parameter variations for the analog device instances based on the extracted layout parameters and the user-defined electrical constraints to identify one or more electrical hotspots in one or more of the analog device instances in the layout design;

performing sensitivity analysis of the one or more electrical hotspots to generate repair hints, the sensitivity analysis including analysis of the effect of mechanical stress due to at least one of well proximity or shallow trench isolation on the electrical behavior of the one or more analog device instances, the repair hints being configured to bring the electrical behavior of the analog device instances within the user-defined electrical constraints while reducing changes to the layout design, the repair hints including one or more diffusion edge modifications of the respective one or more analog device instances associated with the one or more electrical hotspots;

adjusting the layout design based on the repair hints; and

outputting the adjusted layout design.

28. The one or more processor-readable storage media recited in claim 27 , wherein the diffusion edge modifications correspond to a minimum change in saturation current of the one or more analog device instances.