Patent Assignment
Reel/Frame 056675/0285
Merger and Change of Name
Recorded: 2021-06-24
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(84)
Through-Silicon via Impedance Extraction
Patent:
8,448,115 →
Application:
13/526,443 →
Electrical Hotspot Detection, Analysis and Correction
Simulation of Circuits with Repetitive Elements
Placement and Area Adjustment for Hierarchical Groups in Printed Circuit Board Design
Verification Test Set and Test Bench Map Maintenance
Execution Time Profiling for Interpreted Programming Languages
Optical Proximity Correction for Topographically Non-Uniform Substrates
Circuit Instance Variation Probability System and Method
Patent:
8,631,362 →
Application:
13/776,598 →
Virtual Use Of Electronic Design Automation Tools
Layout Decomposition for Triple Patterning Lithography
Debug Environment for a Multi User Hardware Assisted Verification System
Test Data Volume Reduction Based On Test Cube Properties
Test Generation For Test-Per-Clock
Test Bench Transaction Synchronization in a Debugging Environment
Generating Root Cause Candidates for Yield Analysis
Defect Injection for Transistor-Level Fault Simulation
Faulty Chains Identification Without Masking Chain Patterns
Patent:
9,057,762 →
Application:
14/011,995 →
Formal Verification of Booth Multipliers
Test Access Architecture for Multi-Die Circuits
Patent:
9,389,944 →
Application:
14/022,214 →
Test Access Architecture For Stacked Memory And Logic Dies
Patent:
9,689,918 →
Application:
14/030,011 →
Determining Worst-Case Bit Patterns Based Upon Data-Dependent Jitter
Modifying Code to Reduce Redundant or Unnecessary Power Usage
Patent:
10,133,557 →
Application:
14/154,029 →
Scan-Based Test Architecture for Interconnects in Stacked Designs
Test Architecture for Characterizing Interconnects in Stacked Designs
Cloud Services Platform
Single Event Upset Mitigation for Electronic Design Synthesis
Logic Built-In Self-Test with High Test Coverage and Low Switching Activity
Generating A Convergent Circuit Design From A Functional Description Using Entities Having Access To The Functional Description And To Physical Design Information
Modeling Substrate Noise Coupling For Circuit Simulation
Patent:
9,330,226 →
Application:
14/507,831 →
Canonical Forms of Layout Patterns
Compiler for Closed-Loop 1XN Vlsi Design
Tag Based System For Leveraging Design Data
Application:
14/549,224 →
Publication:
US 2015/0149459
Channel Sharing For Testing Circuits Having Non-Identical Cores
Dynamic Shift For Test Pattern Compression
System Design Management
Scan Cell Selection For Partial Scan Designs
Isometric Test Compression With Low Toggling Activity
Connectivity-Aware Layout Data Reduction For Design Verification
Generating Guiding Patterns For Directed Self-Assembly
Low Power Testing Based On Dynamic Grouping Of Scan
Non-Intrusive Software Verification
Prelinked Embedding
Directed Self-Assembly-Aware Layout Decomposition for Multiple Patterning
Statistical Channel Analysis with Correlated Input Patterns
Additive Design of Heat Sinks
Secure Protocol for Chip Authentication
Test Point Insertion For Low Test Pattern Counts
Chip-Scale Electrothermal Analysis
Low Power Corruption Of Memory In Emulation
Execution of Complex Recursive Algorithms
Class Object Handle Tracking
Recognizing and Utilizing Circuit Topology in an Electronic Circuit Design
Coverage Data Interchange
Deterministic Built-In Self-Test Based On Compressed Test Patterns Stored On Chip And Their Derivatives
Guiding Patterns Optimization For Directed Self-Assembly
Leakage Reduction Using Stress-Enhancing Filler Cells
Full-Chip Assessment Of Time-Dependent Dielectric Breakdown
Hybrid Compilation For FPGA Prototyping
Pattern Optical Similarity Determination
Low-Level Sensor Fusion
Test Point-Enhanced Hardware Security
Assertion Statement Check and Debug
Transition Test Generation for Detecting Cell Internal Defects
Circuit Defect Diagnosis Based On Sink Cell Fault Models
Patent:
10,234,502 →
Application:
15/454,909 →
Automatic Axial Thrust Analysis Of Turbomachinery Designs
Communication Circuitry in an Electronic Control Unit
Correcting EUV Crosstalk Effects For Lithography Simulation
Wide-Range Clock Signal Generation For Speed Grading Of Logic Cores
Virtual Ethernet Mutable Port Group Transactor
Target Capture and Replay in Emulation
Content Addressable Memory Modeling in Emulation and Prototyping
Patent:
10,410,713 →
Application:
15/724,262 →
Dynamic Model Generation For Lithographic Simulation
Patent:
10,496,780 →
Application:
15/724,264 →
Removal of Artificial Resonances Using Boundary Element Method
Flow Control In Networking System-On-Chip Verification
Determination Of Structure Function Feature Correlation To Thermal Model Element Layers
Worst Case Eye for Multi-Level Pulse Amplitude Modulated Links
Context-Aware Pattern Matching For Layout Processing
Generic Protocol Analyzer for Circuit Design Verification
Test Application Time Reduction Using Capture-Per-Cycle Test Points
Cell-Aware Diagnostic Pattern Generation for Logic Diagnosis
Efficient And Flexible Network For Streaming Data In Circuits
Patent:
10,788,530 →
Application:
15/925,642 →
Concurrent Testbench and Software Driven Verification
Inter-Cell Bridge Defect Diagnosis
Patent:
10,657,207 →
Application:
15/972,812 →
Reconfigurable Scan Network Defect Diagnosis
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 26, 2012
From: KOURKOULOS, VASILEIOS; SUAYA, ROBERTO
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 028447/0336 →
Assignment of Assignor's Interest
Nov 5, 2012
From: SALEM, RAMI FATHY; EISSA, HAITHAM MOHAMED; ARAFA, AHMED; MOUSA, SHERIF HANY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 029241/0862 →
Assignment of Assignor's Interest
Dec 10, 2012
From: LIN, POLE SHANG; WEN, KUEI SHAN; PERNG, RUEY KUEN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 029438/0835 →
Assignment of Assignor's Interest
Feb 18, 2013
From: GRANIK, YURI; HOLLERBACH, UWE; ADAM, KONSTANTINOS
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 029823/0032 →
Assignment of Assignor's Interest
Mar 1, 2013
From: MEHROTRA, AMIT; SOMANI, ABHISHEK; JOHNSON, KURT; ESTRADA, PAUL
To: BERKELEY DESIGN AUTOMATION, INC.
Reel/Frame 029909/0712 →
Assignment of Assignor's Interest
Mar 18, 2013
From: LI, QIAO; GHOSH, PRADIPTYA
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 030034/0395 →
Assignment of Assignor's Interest
Apr 26, 2013
From: GRIFFIN, BRIAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 030295/0288 →
Assignment of Assignor's Interest
May 17, 2013
From: BALLANCE, MATTHEW
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 030436/0523 →
Assignment of Assignor's Interest
May 17, 2013
From: SUITER, GERALD P.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 030436/0497 →
Assignment of Assignor's Interest
Jun 20, 2013
From: RAJSKI, JANUSZ; LIN, XIJIANG
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 030655/0731 →
Assignment of Assignor's Interest
Jun 21, 2013
From: RAJSKI, JANUSZ; SOLECKI, JEDRZEJ; TYSZER, JERZY; MRUGALSKI, GRZEGORZ
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 030661/0335 →
Assignment of Assignor's Interest
Aug 29, 2013
From: SUNTER, STEPHEN KENNETH
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 031112/0267 →
Assignment of Assignor's Interest
Aug 29, 2013
From: HUANG, YU; CHENG, WU-TUNG; GUO, RUIFENG; SHARMA, MANISH
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 031112/0331 →
Assignment of Assignor's Interest
Sep 6, 2013
From: CASE, MICHAEL L.
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 031153/0091 →
Assignment of Assignor's Interest
Sep 16, 2013
From: AGARWALA, BADRUDDIN; PARIKH, TARAK; BHAT, VIVEK; JOSHI, NEERAJ
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 031215/0741 →
Assignment of Assignor's Interest
Sep 20, 2013
From: BENWARE, ROBERT; CHENG, WU-TUNG; SCHUERMYER, CHRISTOPHER; CHANG, CHEN-YI
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 031249/0680 →
Assignment of Assignor's Interest
Nov 15, 2013
From: SURESH, KRISHNAMURTHY; SELVIDGE, CHARLES W.; GUPTA, SANJAY; JAIN, AMIT
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 031615/0911 →
Nunc Pro Tunc Assignment
Aug 31, 2015
From: BERKELEY DESIGN AUTOMATION, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 036456/0918 →
Assignment of Assignor's Interest
Jul 6, 2017
From: FULLER, RONALD W.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 042926/0811 →
Assignment of Assignor's Interest
Dec 13, 2018
From: CALYPTO DESIGN SYSTEMS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 047766/0077 →