Defect injection for transistor-level fault simulation
View Patent ↗Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.
1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
selecting a circuit element in a circuit netlist of a circuit for defect injection;
determining a defect based on whether the circuit element is a design-intent circuit element or a parasitic circuit element, such that, if the circuit netlist includes at least one design-intent subcircuit netlist but no corresponding physical-implementation subcircuit netlist, passive circuit elements in the at least one design-intent subcircuit netlist are considered as design-intent circuit elements except those having values less than a pre-determined value for each type of circuit elements;
injecting the defect into the circuit netlist; and
simulating the circuit.