Logic built-in self-test with high test coverage and low switching activity

1. A method, comprising:

shifting a low-toggling pseudo-random test pattern into scan chains, the low-toggling pseudo-random test pattern being generated by low-toggling pseudo-random test pattern generation circuitry, low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator;

modifying a plurality of bits in the low-toggling pseudo-random test pattern based on a background test pattern stored in background scan chains to form a weighted pseudo-random test pattern; and

launching the weighted pseudo-random test pattern to test a circuit-under-test.

2. The method recited in claim 1 , wherein the low-toggling pseudo-random test pattern generation circuitry comprises:

a pseudo-random pattern generator; and

circuitry for converting pseudo-random test patterns generated by the pseudo-random pattern generator to the low-toggling pseudo-random test patterns.

3. The method recited in claim 2 , wherein the background test pattern is generated by the pseudo-random pattern generator.

4. The method recited in claim 1 , wherein the plurality of bits are determined based on weight values obtained based on analyzing fault detection probabilities or deterministic test patterns.

5. The method recited in claim 4 , wherein the modifying comprises replacing a bit in the plurality of bits with a bit in the background test pattern if the weight value of the bit is 50% or with a bit outputted from a logic operation that combines two or more bits in the background test pattern if the weight value of the bit is not 50%.

6. The method recited in claim 1 , wherein the modifying is performed in a last shift cycle of the shifting.

7. An integrated circuit, comprising:

low-toggling pseudo-random test pattern generation circuitry, low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator;

scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry;

background chains configurable to shift in a background test pattern; and

weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.

8. The integrated circuit recited in claim 7 , wherein the low-toggling pseudo-random test pattern generation circuitry comprises:

a pseudo-random pattern generator; and

circuitry for converting pseudo-random test patterns generated by the pseudo-random pattern generator to the low-toggling pseudo-random test patterns.

9. The integrated circuit recited in claim 8 , wherein the background test pattern is generated by the pseudo-random pattern generator.

10. The integrated circuit recited in claim 7 , wherein the plurality of bits are determined based on weight values obtained based on analyzing fault detection probabilities or deterministic test patterns.

11. The integrated circuit recited in claim 10 , wherein the modifying performed by the weight insertion circuitry comprises replacing a bit in the plurality of bits with a bit in the background test pattern if the weight value of the bit is 50% or with a bit outputted from a logic operation that combines two or more bits in the background test pattern if the weight value of the bit is not 50%.

12. The integrated circuit recited in claim 7 , wherein the modifying performed by the weight insertion circuitry takes place in a last shift cycle of a shift-in operation of the scan chains.

13. One or more processor-accessible non-transitory storage media storing processor-executable instructions for causing one or more processors to create a design of the integrated circuit, the integrated circuit comprising:

low-toggling pseudo-random test pattern generation circuitry, low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator;

scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry;

background chains configurable to shift in a background test pattern; and

weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.

14. The one or more processor-accessible media recited in claim 13 , wherein the low-toggling pseudo-random test pattern generation circuitry comprises:

a pseudo-random pattern generator; and

circuitry for converting pseudo-random test patterns generated by the pseudo-random pattern generator to the low-toggling pseudo-random test patterns.

15. The one or more processor-accessible media recited in claim 14 , wherein the background test pattern is generated by the pseudo-random pattern generator.

16. The one or more processor-accessible media recited in claim 13 , wherein the plurality of bits are determined based on weight values obtained based on analyzing fault detection probabilities or deterministic test patterns.

17. The one or more processor-accessible media recited in claim 16 , wherein the modifying performed by the weight insertion circuitry comprises replacing a bit in the plurality of bits with a bit in the background test pattern if the weight value of the bit is 50% or with a bit outputted from a logic operation that combines two or more bits in the background test pattern if the weight value of the bit is not 50%.