Full-chip assessment of time-dependent dielectric breakdown

1. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

analyzing a layout design to identify matching patterns that match a pre-calculated pattern in a pattern database, each of pre-calculated patterns in the pattern database having a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution, the model of electric current path generation and evolution assuming field-based hopping conductivity of current carriers; and

determining time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns.

2. The one or more non-transitory computer-readable media recited in claim 1 , wherein the method further comprises:

identifying matching patterns most susceptible to time-dependent dielectric breakdown based on the time-to-failure characteristic values; and

modifying the layout design to fix the matching patterns most susceptible time-dependent dielectric breakdown.

3. The one or more non-transitory computer-readable media recited in claim 1 , wherein the model of electric current path generation and evolution is calibrated with experimental data for a particular manufacture process.

4. The one or more non-transitory computer readable storage device recited in claim 1 , wherein the electric attributes comprise voltage information of the geometric elements.

5. The one or more non-transitory computer readable storage device recited in claim 1 , wherein the electric attributes comprise interconnect types of the geometric elements, the interconnect types comprising power lines, ground lines and signal lines.

6. The one or more non-transitory computer readable storage device recited in claim 1 , wherein the determining is further based on geometric attributes of geometric elements in each of the matching patterns.

7. A method, executed by at least one processor of a computer, comprising:

analyzing a layout design to identify matching patterns that match a pre-calculated pattern in a pattern database, each of pre-calculated patterns in the pattern database having a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution, the model of electric current path generation and evolution assuming field-based hopping conductivity of current carriers; and

determining time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns.

8. The method recited in claim 7 , further comprising:

identifying matching patterns most susceptible to time-dependent dielectric breakdown based on the time-to-failure characteristic values; and

modifying the layout design to fix the matching patterns most susceptible time-dependent dielectric breakdown.

9. The method recited in claim 7 , wherein the model of electric current path generation and evolution is calibrated with experimental data for a particular manufacture process.

10. The method recited in claim 7 , wherein the electric attributes comprise voltage information of the geometric elements.

11. The method recited in claim 7 , wherein the electric attributes comprise interconnect types of the geometric elements, the interconnect types comprising power lines, ground lines and signal lines.

12. The method recited in claim 7 , wherein the determining is further based on geometric attributes of geometric elements in each of the matching patterns.

13. A system comprising:

one or more processors, the one or more processors programmed to perform a method, the method comprising:

analyzing a layout design to identify matching patterns that match a pre-calculated pattern in a pattern database, each of pre-calculated patterns in the pattern database having a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution, the model of electric current path generation and evolution assuming field-based hopping conductivity of current carriers; and

determining time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns.

14. The system recited in claim 13 , wherein the method further comprises:

identifying matching patterns most susceptible to time-dependent dielectric breakdown based on the time-to-failure characteristic values; and

modifying the layout design to fix the matching patterns most susceptible time-dependent dielectric breakdown.

15. The system recited in claim 13 , wherein the model of electric current path generation and evolution is calibrated with experimental data for a particular manufacture process.

16. The system recited in claim 13 , wherein the electric attributes comprise voltage information of the geometric elements.

17. The system recited in claim 13 , wherein the electric attributes comprise interconnect types of the geometric elements, the interconnect types comprising power lines, ground lines and signal lines.

18. The system recited in claim 13 , wherein the determining is further based on geometric attributes of geometric elements in each of the matching patterns.