Flow control in networking system-on-chip verification
A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry. The system employs a backpressure flow control independent of the communication protocol, which can cause the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.
1. A system, comprising:
a reconfigurable hardware modeling device programmed to implement circuitry hardware models, the circuitry hardware models comprising: a hardware model of a circuit design and a hardware model of interface circuitry that converts ingress transaction-level messages to ingress signal-level messages for the hardware model of the circuit design and converts egress signal-level messages dispatched from the hardware model of the circuit design to egress transaction-level messages, wherein the transmitting of the ingress signal-level messages and the egress signal-level messages by the hardware model of the circuit design conforms to a communication protocol; and
a traffic generation device communicating with the reconfigurable hardware modeling device, the traffic generation device being configured to generate and send the ingress transaction-level messages and to receive and analyze the egress transaction-level messages, wherein the reconfigurable hardware modeling device and the traffic generation device employ a backpressure flow control independent of the communication protocol, the backpressure flow control causing the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.
2. The system recited in claim 1 , wherein the reconfigurable hardware modeling device is a hardware emulator or an FPGA-based prototyping device.
3. The system recited in claim 1 , wherein the traffic generation device is implemented at least in part by a network traffic tool, the network traffic tool being implemented by a virtual machine running on a computer.
4. The system recited in claim 3 , wherein the traffic generation device comprises a virtual interface and an interface software model, the virtual interface being an interface between the virtual machine and a host program running on the computer, the interface software model being coupled to the hardware model of interface circuitry.
5. The system recited in claim 1 , wherein the circuit design has one or more ports for sending and/or receiving message packets.
6. The system recited in claim 1 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.
7. The system recited in claim 1 , wherein the backpressure flow control comprises checking status of one or more of the one or more message buffers by the traffic generation device before sending a message.
8. The system recited in claim 1 , wherein the backpressure flow control comprises sending a message to the traffic generation device.
9. The system recited in claim 1 , wherein the traffic generation device communicates with the reconfigurable hardware modeling device through one or more physical communication channels.
10. The system recited in claim 1 , wherein the backpressure flow control comprises sending a dedicated message frame that includes a transmit ON field and a transmit OFF field.
11. The system recited in claim 1 , wherein the backpressure flow control comprises generating a saturation signal that identifies portions of a transmit buffer having transmission packets already read by a host program and also identifying portions of the transmit buffer having transmission packets waiting to be read by the host program.