Channel sharing for testing circuits having non-identical cores
View Patent ↗Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.
1. A method, executed by at least one processor of a computer, comprising:
generating compressed test patterns for a plurality of circuit blocks comprising identical and non-identical circuit blocks, wherein the plurality of circuit blocks are components of a circuit design, each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns and a compactor configured to compact test response data, and the generating comprises determining control data for each of non-identical circuit blocks in the plurality of circuit blocks, the control data further being for control data input channels that are respectively dedicated to each of the non-identical circuit blocks and that are separate and different from each other, wherein a plurality of the identical circuit blocks in the plurality of circuit blocks share the same control data input channel; and
storing the compressed test patterns and the control data.
2. The method recited in claim 1 , wherein the control data for each of non-identical circuit blocks in the plurality of circuit blocks comprise mask control bits for the compactor in the each of non-identical circuit blocks in the plurality of circuit blocks.
3. The method recited in claim 1 , wherein one or more of the non-identical circuit blocks have multiple instances.
4. The method recited in claim 1 , wherein some circuit blocks in the plurality of circuit blocks belong to an IP (intellectual property) core.
5. The method recited in claim 1 , further comprising:
shifting the compressed test patterns into the decompressors in the plurality of circuit blocks through shared test data-only input channels; and
shifting the control data into registers in each of non-identical circuit blocks in the plurality of circuit blocks through the control data input channels, the non-identical circuit blocks using different control data input channels.
6. The method recited in claim 5 , wherein the plurality of identical circuit blocks in the plurality of circuit blocks comprises a first set of identical circuit blocks that use a first control data input channel, and wherein a second set of identical circuit blocks use a second control data input channel that is different from the first control data input channel.
7. The method recited in claim 1 , wherein the decompressor is a linear finite-state machine.
8. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
generating compressed test patterns for a plurality of circuit blocks comprising identical and non-identical circuit blocks, wherein the plurality of circuit blocks are components of a circuit design, each of the plurality of circuit blocks has a decompressor configured to decompress the compressed test patterns and a compactor configured to compact test response data, and the generating comprises determining control data for each of non-identical circuit blocks in the plurality of circuit blocks, the control data further being for control data input channels that are respectively dedicated to each of the non-identical circuit blocks and that are separate and different from each other, wherein a plurality of the identical circuit blocks in the plurality of circuit blocks uses the same control data input channel; and
storing the compressed test patterns and the control data.
9. The one or more non-transitory computer-readable media recited in claim 8 , wherein the control data for each of non-identical circuit blocks in the plurality of circuit blocks comprise mask control bits for the compactor in the each of non-identical circuit blocks in the plurality of circuit blocks.
10. The one or more non-transitory computer-readable media recited in claim 8 , wherein some circuit blocks in the plurality of circuit blocks belong to an IP (intellectual property) core.
11. The one or more non-transitory computer-readable media recited in claim 8 , wherein the method further comprises:
shifting the compressed test patterns into the decompressors in the plurality of circuit blocks through shared test data-only input channels; and
shifting the control data into registers in each of non-identical circuit blocks in the plurality of circuit blocks through the control data input channels, the non-identical circuit blocks using different control data input channels.
12. The one or more non-transitory computer-readable media recited in claim 11 , wherein the plurality of identical circuit blocks in the plurality of circuit blocks comprises a first set of identical circuit blocks that shares a first control data input channel for the control data, and wherein a second set of identical circuit blocks in the plurality of circuit blocks shares a second control data input channel for the control data that is different from the first control data input channel.
13. The one or more non-transitory computer-readable media recited in claim 8 , wherein the decompressor is a linear finite-state machine.
14. An integrated circuit, comprising:
a plurality of circuit blocks comprising identical and non-identical circuit blocks, wherein each of the plurality of circuit blocks comprises:
a decompressor configured to decompress compressed test patterns, and
a compactor configured to compact test response data;
first input channels for shifting in only compressed test patterns, wherein the first input channels are shared by the decompressors in the plurality of circuit blocks and the compressed test patterns are generated for the plurality of circuit blocks; and
second input channels for shifting in control data, wherein different non-identical circuit blocks in the plurality of circuit blocks are connected to separate and different ones of the input channels from among the second input channels, and wherein identical circuit blocks in the plurality of circuit blocks share input channels in the second input channels.
15. The integrated circuit recited in claim 14 , wherein the plurality of identical circuit blocks in the plurality of circuit blocks comprises a first set of identical circuit blocks that uses a first control data input channel, and wherein a second set of identical circuit blocks uses a second control data input channel that is different from the first control data input channel.
16. The integrated circuit recited in claim 14 , wherein some circuit blocks in the plurality of circuit blocks belong to an IP (intellectual property) core.
17. The integrated circuit recited in claim 14 , wherein the decompressor is a linear finite-state machine.
18. The integrated circuit recited in claim 14 , wherein the control data for each of non-identical circuit blocks in the plurality of circuit blocks comprise mask control bits for the compactor in the each of non-identical circuit blocks in the plurality of circuit blocks.
19. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to create or to modify a design of an integrated circuit, the integrated circuit comprising:
a plurality of circuit blocks comprising identical and non-identical circuit blocks, wherein each of the plurality of circuit blocks comprises:
a decompressor configured to decompress compressed test patterns, and
a compactor configured to compact test response data;
first input channels for shifting in only compressed test patterns, wherein the first input channels are shared by the decompressors in the plurality of circuit blocks and the compressed test patterns are generated for the plurality of circuit blocks; and
second input channels for shifting in control data, wherein different non-identical circuit blocks in the plurality of circuit blocks are connected to separate and different ones of the input channels from among the second input channels, and wherein identical circuit blocks in the plurality of circuit blocks share input channels in the second input channels.
20. The one or more non-transitory computer-readable media recited in claim 19 , wherein the plurality of identical circuit blocks in the plurality of circuit blocks comprises a first set of identical circuit blocks that uses a first control data input channel, and wherein a second set of identical circuit blocks uses a second control data input channel that is different from the first control data input channel.
21. The one or more non-transitory computer-readable media recited in claim 19 , wherein some circuit blocks in the plurality of circuit blocks belong to an IP (intellectual property) core.
22. The one or more non-transitory computer-readable media recited in claim 19 , wherein the decompressor is a linear finite-state machine.
23. The one or more non-transitory computer-readable media recited in claim 19 , wherein the control data for each of non-identical circuit blocks in the plurality of circuit blocks comprise mask control bits for the compactor in the each of non-identical circuit blocks in the plurality of circuit blocks.