Compiler for closed-loop 1×N VLSI design
View Patent ↗Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
1. A method, comprising:
inputting, by a computing device, a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block;
generating, by the computing device, a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, or a flattened netlist; and
generating, by the computing device and via a 1×N compiler, a gate-level representation of the integrated circuit design based on the physical design representation, wherein the generating comprises converting the physical design representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the gate-level representation.
2. The method of claim 1 , further comprising generating, by the computing device, a second behavioral representation of the design via the physical design representation.
3. The method of claim 2 , further comprising altering, by the computing device, an element of the 1×N building block of the physical design representation via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool.
4. The method of claim 3 , further comprising generating, by the computing device, a second gate-level representation of the integrated circuit design via the physical design representation, wherein the second gate-level representation and the second behavioral representation include the altering of the element.
5. The method of claim 4 , further comprising generating, by the computing device, a helper script, wherein the creating the gate-level and physical design representations comprise creating a gate-level RTL description and a physical design netlist, respectively.
6. The method of claim 1 , further comprising:
generating a second physical design representation wherein the generating the second physical design representation comprises transforming logical constructs of the 1×N building block of the gate-level representation to physical constructs of the 1×N building block for the second physical design representation, wherein further the transforming the logical constructs to the physical constructs comprises creating the physical constructs with a routing tool.
7. A method comprising:
inputting, by a computing device, a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block;
generating, by the computing device, a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, or a flattened netlist;
generating, by the computing device and via a 1×N compiler, a gate-level representation of the integrated circuit design via the physical design representation, wherein the generating comprises converting the physical design representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the gate-level representation;
generating, by the computing device, a second behavioral representation of the design via the physical design representation, wherein the generating comprises converting the physical design representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the second behavioral representation; and
checking, by the computing device, for at least one of a capacitance violation, a drive strength requirement, or a physical design rule requirement for at least one of the creating the physical design representation, the second behavioral representation, and a second gate-level representation of the integrated circuit design.
8. A method comprising:
inputting, by a computing device, a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block;
generating, by the computing device, a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, or a flattened netlist;
generating, by the computing device and via a 1×N compiler, a gate-level representation of the integrated circuit design via the physical design representation, wherein the generating comprises converting the physical design representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the gate-level representation; and
generating, by the computing device, a second behavioral representation of the design via the physical design representation, wherein the generating the second behavioral representation comprises converting the physical design representation into one or more 1×N building blocks and detecting an alteration of an element of the one or more 1×N building blocks by comparison of the one or more 1×N building blocks with a previously generated one or more 1×N building blocks.
9. A non-transitory computer-readable medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform a method, the method comprising:
inputting a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block;
generating a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, or a flattened netlist; and
generating, via a 1×N compiler, a gate-level representation of the integrated circuit design via the physical design representation, wherein the generating comprises converting the physical design representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the gate-level representation.
10. The non-transitory computer-readable medium of claim 9 , wherein the method further comprises:
generating a second behavioral representation of the design via the physical design representation.
11. The non-transitory computer-readable medium of claim 10 , wherein the method further comprises:
altering an element of the one or more 1×N building blocks of the physical design representation via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool.
12. The non-transitory computer-readable medium of claim 11 , wherein the method further comprises:
generating a second gate-level representation of the integrated circuit design via the physical design representation, wherein the second gate-level representation and the second behavioral representation include the altering of the element.
13. The non-transitory computer-readable medium of claim 12 , wherein the method further comprises:
generating a helper script, wherein the creating the gate-level and physical design representations comprise creating a gate-level RTL description and a physical design netlist, respectively.
14. The non-transitory computer-readable medium of claim 10 , wherein the method further comprises:
checking for at least one of a capacitance violation, a drive strength requirement, or a physical design rule requirement for at least one of the creating the physical design representation, the second behavioral representation, and a second gate-level representation of the integrated circuit design.
15. The non-transitory computer-readable medium of claim 10 , wherein the generating the second behavioral representation comprises converting the physical design representation into one or more 1×N building blocks and detecting an alteration of an element of the one or more 1×N building blocks by comparison of the one or more 1×N building blocks with a previously generated one or more 1×N building blocks.
16. The non-transitory computer-readable medium of claim 9 , further comprising:
generating a second physical design representation, wherein the generating the second physical design representation comprises transforming logical constructs of the of the gate-level representation to physical constructs for the second physical design representation, wherein transforming the logical constructs to the physical constructs comprises converting the logical constructs of the gate-level representation into one or more 1×N building blocks and compiling the 1×N building blocks, via the 1×N compiler, into the physical constructs of the second physical design.