Single event upset mitigation for electronic design synthesis

1. A method comprising:

retrieving, from one or more memory, timing data for a plurality of signal paths within a circuit design;

determining, based on the timing data, that the circuit design does not meet a predetermined single event upset susceptibility requirement;

generating a modified circuit design by adding, in response to the determining, one or more delays to the plurality of signal paths, wherein the adding of the one or more delays comprises reducing a strength of a driver on one of the plurality of signal paths, adding a buffer in the one of the plurality of signal paths, or a combination thereof; and

storing the modified circuit design to the one or more memory.

2. The method of claim 1 , further comprising:

receiving new timing data for the plurality of signal paths within the modified circuit design;

determining, based on the new timing data, that the modified circuit design does not meet the predetermined single event upset susceptibility requirement;

generating, in response to the modified circuit design not meeting the predetermined single event upset susceptibility requirement, a second modified circuit design by adding one or more additional delays to the plurality of signal paths; and

storing the second modified circuit design to the one or more memory.

3. The method of claim 1 , further comprising:

performing place-and-route of the modified circuit design to produce a placed-and-routed circuit design;

receiving new timing data for the plurality of signal paths within the placed-and-routed circuit design;

determining, based on the new timing data, that the placed-and-routed circuit design does not meet the predetermined single event upset susceptibility requirement; and

generating, in response to the placed-and-routed circuit design not meeting the predetermined single event upset susceptibility requirement, a second placed-and-routed circuit design by adding one or more additional delays to the plurality of signal paths; and

storing the second placed-and-routed circuit design to the one or more memory.

4. The method of claim 1 , wherein the determining that the circuit design does not meet the predetermined single event upset susceptibility requirement, includes:

determining that positive slack for each of the plurality of signal paths is greater than a duration associated with the predetermined single event upset susceptibility requirement.

5. The method of claim 1 , wherein the circuit design comprises a gate-level design produced from synthesis of a register transfer level design or produced from a place-and-route process performed on an un-routed gate-level design.

6. The method of claim 1 , further comprising:

generating the timing data by performing static timing analysis of the circuit design.

7. The method of claim 1 , wherein the one or more delays are added such that the plurality of signal paths in the modified circuit design have zero static timing slack.

8. A method comprising:

receiving a predetermined single event upset susceptibility threshold value associated with a circuit design;

identifying, from timing data produced by a timing analysis of the circuit design, a signal path within the circuit design that has positive slack; and

adding, using a computer implemented modification tool, a delay to the signal path, based upon the predetermined single event upset susceptibility threshold value, by modifying or adding one or more circuit components in the signal path, wherein the modifying or the adding of the one or more circuit components in the signal path includes reducing a strength of a driver on the signal path, adding a buffer in the signal path, or a combination thereof.

9. The method of claim 8 , further comprising:

receiving new timing data produced by a new timing analysis of a placed-and-routed circuit design produced by placement and routing of the circuit design;

identifying, from the new timing data, a placed-and-routed signal path within the placed-and-routed circuit design that has positive slack; and

adding a new delay to the placed-and-routed signal path, based upon the predetermined single event upset susceptibility threshold value, by modifying or adding one or more additional circuit components in the placed-and-routed signal path.

10. The method of claim 8 , wherein the adding of the delay to the signal path is based upon the positive slack being greater than a duration associated with the predetermined single event upset susceptibility threshold.

11. The method of claim 8 , wherein the circuit design comprises a gate-level design synthesized by a Register Transfer Level synthesis process or a place-and-route process.

12. An apparatus comprising:

a microprocessor and one or more memory storing software instructions, that when executed by the microprocessor, cause the apparatus to:

retrieve, from the one or more memory, timing data for a plurality of signal paths within a circuit design;

determine, based on the timing data, that the circuit design does not meet a predetermined single event upset susceptibility requirement;

generate a modified circuit design by adding, in response to the determination that the circuit design does not meet the predetermined single event upset susceptibility requirement, one or more delays to the plurality of signal paths, wherein the adding of the one or more delays comprises reducing a strength of a driver on one of the plurality of signal paths, adding a buffer in the one of the plurality of signal paths, or a combination thereof; and

store the modified circuit design to the one or more memory.

13. The apparatus of claim 12 , wherein the software instructions, when executed by the microprocessor, further cause the apparatus to:

perform static timing analysis on the modified circuit design to generate new timing data for the plurality of signal paths;

determine, based on the new timing data, that the modified circuit design does not meet the predetermined single event upset susceptibility requirement;

generate, in response to the modified circuit design not meeting the predetermined single event upset susceptibility requirement, a second modified circuit design by adding one or more additional delays to the plurality of signal paths; and

store the second modified circuit design to the one or more memory.

14. The apparatus of claim 12 , wherein the software instructions, when executed by the microprocessor, further cause the apparatus to:

perform place-and-route of the modified circuit design to produce a placed-and-routed circuit design;

perform static timing analysis on the placed-and-routed circuit design to generate new timing data for the plurality of signal paths;

determine, based on the new timing data, that the placed-and-routed circuit design does not meet the predetermined single event upset susceptibility requirement; and

generate, in response to the placed-and-routed circuit design not meeting the predetermined single event upset susceptibility requirement, a second placed-and-routed circuit design by adding one or more additional delays to the plurality of signal paths; and

store the second placed-and-routed circuit design to the one or more memory.

15. The apparatus of claim 12 , wherein the software instructions, when executed by the microprocessor, further cause the apparatus to:

determine that the circuit design does not meet the predetermined single event upset susceptibility requirement by determining that positive slack for each of the plurality of signal paths is greater than a duration associated with the predetermined single event upset susceptibility requirement.

16. The apparatus of claim 12 , wherein the circuit design comprises a gate-level design produced from synthesis of a register transfer level design or produced from place-and-route process.

17. The apparatus of claim 12 , wherein the one or more delays are added such that the plurality of signal paths in the modified circuit design have zero static timing slack.