Generating guiding patterns for directed self-assembly

1. One or more processor-readable storage devices storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations of the two or more via-type features;

B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional function and comprises a first portion representing interactions between via-type features in the via-type feature group and a second portion representing wall effects of the guiding pattern;

C: computing simulated locations of the two or more via-type features based on the potential energy function;

D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and

F: repeating operations A through D until one of one or more termination conditions is met.

2. The one or more processor-readable storage devices recited in claim 1 , wherein initial positions of the seeding positions are centers of the corresponding target locations.

3. The one or more processor-readable storage devices recited in claim 1 , wherein the one or more termination conditions comprise whether the simulated locations match the targeted locations.

4. The one or more processor-readable storage devices recited in claim 1 , wherein the one or more termination conditions comprise number of iterations of operations A through D reaches a predetermined number.

5. The one or more processor-readable storage devices recited in claim 1 , wherein the via-type feature group is DSA (Directed-Self-Assembly)-compliant.

6. The one or more processor-readable storage devices recited in claim 1 , wherein the constructing is further based on area ratio information of a di-block copolymer.

7. The one or more processor-readable storage devices recited in claim 1 , wherein the constructing comprises generating polygons centered at the seeding positions.

8. A method, executed by at least one processor of a computer, comprising:

A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations of the two or more via-type features;

B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional function and comprises a first portion representing interactions between via-type features in the via-type feature group and a second portion representing wall effects of the guiding pattern;

C: computing simulated locations of the two or more via-type features based on the potential energy function;

D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and

F: repeating operations A through D until one of one or more termination conditions is met.

9. The method recited in claim 8 , wherein initial positions of the seeding positions are centers of the corresponding target locations.

10. The method recited in claim 8 , wherein the one or more termination conditions comprise whether the simulated locations match the targeted locations.

11. The method recited in claim 8 , wherein the one or more termination conditions comprise number of iterations of operations A through D reaches a predetermined number.

12. The method recited in claim 8 , wherein the via-type feature group is DSA (Directed-Self-Assembly) compliant.

13. The method recited in claim 8 , wherein the constructing is further based on area ratio information of a di-block copolymer.

14. The method recited in claim 8 , wherein the constructing comprises generating polygons centered at the seeding positions.

15. A system comprising:

one or more processors, the one or more processors programmed to perform a method, the method comprising:

A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations of the two or more via-type features;

B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional function and comprises a first portion representing interactions between via-type features in the via-type feature group and a second portion representing wall effects of the guiding pattern;

C: computing simulated locations of the two or more via-type features based on the potential energy function;

D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and

F: repeating operations A through D until one of one or more termination conditions is met.

16. The system recited in claim 15 , wherein initial positions of the seeding positions are centers of the corresponding target locations.

17. The system recited in claim 15 , wherein the one or more termination conditions comprise whether the simulated locations match the targeted locations, wherein the one or more termination conditions comprise number of iterations of operations A through D reaches a predetermined number, or both.

18. The system recited in claim 15 , wherein the via-type feature group is DSA (Directed-Self-Assembly) compliant.

19. The system recited in claim 15 , wherein the constructing is further based on area ratio information of a di-block copolymer.

20. The system recited in claim 15 , wherein the constructing comprises generating polygons centered at the seeding positions.