Transition test generation for detecting cell internal defects
Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.
1. A method, executed by at least one processor of a computer, comprising:
determining, by the at least one processor and based on a gate-level representation of a circuit design, an assignment for two consecutive clock cycles at inputs of a complex cell in the circuit design including a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell, the complex cell being represented by two or more logic gates in the gate-level representation, and the sensitizing meaning that the output has no transition if the one of the inputs has no transition while the remaining part of the assignment does not change;
deriving, by the at least one processor and based on the gate-level representation, a test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to second clock cycle of the two consecutive clock cycles from the output to an observation point; and
storing, by the at least one processor, the test pattern, wherein the test pattern is thereafter used to test integrated circuit devices fabricated based, at least in part, on the circuit design, by applying the test pattern to the integrated circuit devices.
2. The method recited in claim 1 , wherein the gate-level representation is a gate-level netlist.
3. The method recited in claim 1 , further comprising:
repeating the determining, the deriving and the storing by the at least one processor by replacing the first transition with a third transition, the third transition being opposite to the first transition.
4. The method recited in claim 1 , further comprising:
repeating the determining, the deriving and the storing by the at least one processor by replacing the second transition with a third transition, the third transition being opposite to the second transition.
5. The method recited in claim 1 , further comprising:
repeating the determining, the deriving and the storing by the at least one processor by replacing the second transition with a third transition at a second output of the complex cell.
6. The method recited in claim 1 , wherein the method is performed by executing an automatic test pattern generation (ATPG) tool in the computer.
7. The method recited in claim 1 , wherein the observation point is a primary output or a scan cell.
8. One or more non-transitory processor-readable media storing processor-executable instructions for causing one or more processors to perform a method, the method comprising:
determining, based on a gate-level representation of a circuit design, an assignment for two consecutive clock cycles at inputs of a complex cell in the circuit design including a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell, the complex cell being represented by two or more logic gates in the gate-level representation, and the sensitizing meaning that the output has no transition if the one of the inputs has no transition while the remaining part of the assignment does not change;
deriving, based on the gate-level representation, a test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to second clock cycle of the two consecutive clock cycles from the output to an observation point; and
storing the test pattern, wherein the test pattern is thereafter used to test integrated circuit devices fabricated based, at least in part, on the circuit design, by applying the test pattern to the integrated circuit device.
9. The one or more non-transitory processor-readable media recited in claim 8 , wherein the gate-level representation is a gate-level netlist.
10. The one or more non-transitory processor-readable media recited in claim 8 , wherein the method further comprises:
repeating the determining, the deriving and the storing by replacing the first transition with a third transition, the third transition being opposite to the first transition.
11. The one or more non-transitory processor-readable media recited in claim 8 , wherein the method further comprises:
repeating the determining, the deriving and the storing by replacing the second transition with a third transition, the third transition being opposite to the second transition.
12. The one or more non-transitory processor-readable media recited in claim 8 , wherein the method further comprises:
repeating the determining, the deriving and the storing by replacing the second transition with a third transition at a second output of the complex cell.
13. The one or more non-transitory processor-readable media recited in claim 8 , wherein the processor-executable instructions are a part of an automatic test pattern generation (ATPG) tool.
14. The one or more non-transitory processor-readable media recited in claim 8 , wherein the observation point is a primary output or a scan cell.
15. A system, comprising:
one or more processors, the one or more processors programmed to perform a method, the method comprising:
determining, based on a gate-level representation of a circuit design, an assignment for two consecutive clock cycles at inputs of a complex cell in the circuit design including a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell, the complex cell being represented by two or more logic gates in the gate-level representation, and the sensitizing meaning that the output has no transition if the one of the inputs has no transition while the remaining part of the assignment does not change;
deriving, based on the gate-level representation, a test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to second clock cycle of the two consecutive clock cycles from the output to an observation point; and
storing the test pattern, wherein the test pattern is thereafter used to test integrated circuit devices fabricated based, at least in part, on the circuit design, by applying the test pattern to the integrated circuit device.
16. The system recited in claim 15 , wherein the gate-level representation is a gate-level netlist.
17. The system recited in claim 15 , wherein the method further comprises:
repeating the determining, the deriving and the storing by replacing the first transition with a third transition, the third transition being opposite to the first transition.
18. The system recited in claim 15 , wherein the method further comprises:
repeating the determining, the deriving and the storing by replacing the second transition with a third transition, the third transition being opposite to the second transition.
19. The system recited in claim 15 , wherein the method further comprises:
repeating the determining, the deriving and the storing by replacing the second transition with a third transition at a second output of the complex cell.