Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
View Patent ↗A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints.
1. A method comprising:
forming, by a computing system, multiple circuit design entities, each including a different set of gates in a gate-level implementation of an electronic system;
determining, by the computing system, a physical layout for the circuit design entities based, at least in part, on characteristics of the sets of gates in the circuit design entities; and
generating, by the computing system, a physical design implementation for the electronic system based, at least in part, on the physical layout for the circuit design entities.
2. The method of claim 1 , wherein forming the circuit design entities further comprises:
partitioning a functional description of the electronic system; and
synthesizing each partition of the functional description into the different sets of gates, which are included in the circuit design entities.
3. The method of claim 2 , wherein each circuit design entity includes one or more of the partitions of the functional description corresponding to the set of gates included within that circuit design entity or a link to the one or more of the partitions of the functional description.
4. The method of claim 2 , wherein determining the physical layout for the multiple entities further comprises resynthesizing at least one of the partitions of the functional description associated with one or more of the circuit design entities into one or more new sets of gates, wherein determining the physical layout for the multiple entities is based, at least in part, on the new sets of gates.
5. The method of claim 2 , wherein determining the layout for the multiple entities further comprises:
repartitioning the functional description of the electronic system; and
resynthesizing each repartition of the functional description into new sets of gates, which are included in the circuit design entities corresponding to the repartitions of the functional description.
6. The method of claim 1 , wherein generating the physical design implementation for the electronic system is performed when the physical layout for the circuit design entities satisfies a set of one or more design constraints for the electronic system.
7. The method of claim 1 , wherein the characteristics of the sets of gates in the circuit design entities includes, for each circuit design entity, aggregate parameters for the set of gates corresponding to that circuit design entity.
8. A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to form multiple circuit design entities, each including a different set of gates in a gate-level implementation of an electronic system, wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to determine a physical layout for the circuit design entities based, at least in part, on characteristics of the sets of gates in the circuit design entities, and generate a physical design implementation for the electronic system based, at least in part, on the physical layout for the circuit design entities.
9. The system of claim 8 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to partition a functional description of the electronic system, and synthesize each partition of the functional description into the different sets of gates, which are included in the circuit design entities.
10. The system of claim 9 , wherein each circuit design entity includes one or more of the partitions of the functional description corresponding to the set of gates included within that circuit design entity or a link to the one or more of the partitions of the functional description.
11. The system of claim 9 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to determine the physical layout for the multiple entities by resynthesizing at least one of the partitions of the functional description associated with one or more of the circuit design entities into one or more new sets of gates, wherein determining the physical layout for the multiple entities is based, at least in part, on the new sets of gates.
12. The system of claim 8 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to generate the physical design implementation for the electronic system when the physical layout for the circuit design entities satisfies a set of one or more design constraints for the electronic system.
13. The system of claim 8 , wherein the characteristics of the sets of gates in the circuit design entities includes, for each circuit design entity, aggregate parameters for the set of gates corresponding to that circuit design entity.
14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
forming multiple circuit design entities, each including a different set of gates in a gate-level implementation of an electronic system;
determining a physical layout for the circuit design entities based, at least in part, on characteristics of the sets of gates in the circuit design entities; and
generating a physical design implementation for the electronic system based, at least in part, on the physical layout for the circuit design entities.
15. The apparatus of claim 14 , wherein forming the circuit design entities further comprises:
partitioning a functional description of the electronic system; and
synthesizing each partition of the functional description into the different sets of gates, which are included in the circuit design entities.
16. The apparatus of claim 15 , wherein each circuit design entity includes one or more of the partitions of the functional description corresponding to the set of gates included within that circuit design entity or a link to the one or more of the partitions of the functional description.
17. The apparatus of claim 15 , wherein determining the physical layout for the multiple entities further comprises resynthesizing at least one of the partitions of the functional description associated with one or more of the circuit design entities into one or more new sets of gates, wherein determining the physical layout for the multiple entities is based, at least in part, on the new sets of gates.
18. The apparatus of claim 15 , wherein determining the layout for the multiple entities further comprises:
repartitioning the functional description of the electronic system; and
resynthesizing each repartition of the functional description into new sets of gates, which are included in the circuit design entities corresponding to the repartitions of the functional description.
19. The apparatus of claim 14 , wherein generating the physical design implementation for the electronic system is performed when the physical layout for the circuit design entities satisfies a set of one or more design constraints for the electronic system.
20. The apparatus of claim 14 , wherein the characteristics of the sets of gates in the circuit design entities includes, for each circuit design entity, aggregate parameters for the set of gates corresponding to that circuit design entity.