Wide-range clock signal generation for speed grading of logic cores
An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.
1. An integrated circuit, comprising:
test circuitry comprising scan chains and a test controller; and
wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry, the wide-range clock signal generation circuitry configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading, the wide-range test clock signal being generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.
2. The integrated circuit recited in claim 1 , wherein the phase-locked loop circuitry comprises a first phase-locked loop circuit and a second phase-locked loop circuit, and the frequency divider circuitry comprises a first frequency divider and a second frequency divider, wherein the first phase-locked loop circuit generates a high speed clock signal based on the test clock signal, the first frequency divider generates a preliminary tunable clock signal based on the high speed clock signal and the frequency setting signal, the second phase-locked loop circuit generates a tunable clock signal based on the preliminary tunable clock signal, and the second frequency divider generates the wide-range clock signal based on the tunable clock signal and the frequency range selection signal.
3. The integrated circuit recited in claim 1 , wherein the wide-range clock signal generation circuitry further comprises:
final test clock signal generation circuitry, the final test clock signal generation circuitry combining the test clock signal with the wide-range clock signal to generate a final test clock signal, the final test clock signal being used by the scan-based test circuitry to conduct the structural delay test.
4. The integrated circuit recited in claim 1 , wherein the structural delay test uses a launch-off-capture method.
5. The integrated circuit recited in claim 1 , wherein the test controller comprises a pseudo-random test pattern generator.
6. The integrated circuit recited in claim 1 , wherein the test controller comprises a decompressor for deterministic tests.
7. The integrated circuit recited in claim 1 , wherein the test controller comprises a speed grading controller configured to generate the frequency range selection signal and the frequency setting signal.
8. One or more non-transitory computer-readable media storing computer-executable instructions, that, when executed, cause a computer to create a system for on-chip speed grading in an electronic circuit design by:
creating test circuitry comprising scan chains and a test controller; and
creating wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry, the wide-range clock signal generation circuitry configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading, the wide-range test clock signal being generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.
9. The one or more computer-readable media recited in claim 8 , wherein the phase-locked loop circuitry comprises a first phase-locked loop circuit and a second phase-locked loop circuit, and the frequency divider circuitry comprises a first frequency divider and a second frequency divider, wherein the first phase-locked loop circuit generates a high speed clock signal based on the test clock signal, the first frequency divider generates a preliminary tunable clock signal based on the high speed clock signal and the frequency setting signal, the second phase-locked loop circuit generates a tunable clock signal based on the preliminary tunable clock signal, and the second frequency divider generates the wide-range clock signal based on the tunable clock signal and the frequency range selection signal.
10. The one or more non-transitory computer-readable media recited in claim 8 , wherein the wide-range clock signal generation circuitry further comprises:
final test clock signal generation circuitry, the final test clock signal generation circuitry combining the test clock signal with the wide-range clock signal to generate a final test clock signal, the final test clock signal being used by the scan-based test circuitry to conduct the structural delay test.
11. The one or more non-transitory computer-readable media recited in claim 8 , wherein the structural delay test uses a launch-off-capture method.
12. The one or more non-transitory computer-readable media recited in claim 8 , wherein the test controller comprises a pseudo-random test pattern generator.
13. The one or more non-transitory computer-readable media recited in claim 8 , wherein the test controller comprises a decompressor for deterministic tests.
14. The one or more non-transitory computer-readable media recited in claim 8 , wherein the test controller comprises a speed grading controller configured to generate the frequency range selection signal and the frequency setting signal.