Context-aware pattern matching for layout processing
Aspects of the disclosed technology relate to techniques of context-aware pattern matching and processing. A circuit design is analyzed to identity circuit components of interest. Reference layout patterns that are associated with the circuit components of interest are extracted from a layout design based on the association of circuit components of the circuit design with geometric elements of the layout design. Pattern matching is performed to identify layout patterns that match the reference layout patterns. The identified layout patterns are then processed.
1. One or more non-transitory computer-readable media storing computer-executable instructions, the computer-executable instructions, when executed, causing one or more processors to perform a method, the method comprising:
receiving a circuit design, circuit components of the circuit design being associated with geometric elements of a layout design;
analyzing the circuit design to identity circuit components of interest;
extracting reference layout patterns from the layout design that are associated with the circuit components of interest, and storing the extracted reference layout patterns in a reference pattern library;
performing pattern matching to identify layout patterns that match the reference layout patterns;
processing the layout patterns; and
reporting results of the processing.
2. The one or more non-transitory computer-readable media recited in claim 1 , wherein the extracting comprises:
determining preliminary reference layout patterns that are associated with the circuit components of interest; and
compressing the preliminary reference layout patterns to generate reference layout patterns.
3. The one or more non-transitory computer-readable media recited in claim 1 , wherein the processing comprises adding dummy fills to the layout patterns.
4. The one or more non-transitory computer-readable media recited in claim 3 , wherein the dummy fills are added based on orientations of the layout patterns.
5. The one or more non-transitory computer-readable media recited in claim 1 , wherein the processing comprises performing layout decomposition for multiple-patterning.
6. The one or more non-transitory computer-readable media recited in claim 1 , wherein the pattern matching comprises fuzzy pattern matching.
7. A method, executed by at least one processor of a computer, comprising:
receiving a circuit design, circuit components of the circuit design being associated with geometric elements of a layout design;
analyzing the circuit design to identity circuit components of interest;
extracting reference layout patterns from the layout design that are associated with the circuit components of interest, and storing the extracted reference layout patterns in a reference pattern library;
performing pattern matching to identify layout patterns that match the reference layout patterns;
processing the layout patterns; and
reporting results of the processing.
8. The method recited in claim 7 , wherein the extracting comprises:
determining preliminary reference layout patterns that are associated with the circuit components of interest; and
compressing the preliminary reference layout patterns to generate reference layout patterns.
9. The method recited in claim 7 , wherein the processing comprises adding dummy fills to the layout patterns.
10. The method recited in claim 9 , wherein the dummy fills are added based on orientations of the layout patterns.
11. The method recited in claim 7 , wherein the processing comprises performing layout decomposition for multiple-patterning.
12. The method recited in claim 7 , wherein the pattern matching comprises fuzzy pattern matching.
13. A system comprising:
one or more processors, the one or more processors programmed to perform a method, the method comprising:
receiving a circuit design, circuit components of the circuit design being associated with geometric elements of a layout design;
analyzing the circuit design to identity circuit components of interest;
extracting reference layout patterns from the layout design that are associated with the circuit components of interest, and storing the extracted reference layout patterns in a reference pattern library;
performing pattern matching to identify layout patterns that match the reference layout patterns;
processing the layout patterns; and
reporting results of the processing.
14. The system recited in claim 13 , wherein the extracting comprises:
determining preliminary reference layout patterns that are associated with the circuit components of interest; and
compressing the preliminary reference layout patterns to generate reference layout patterns.
15. The system recited in claim 13 , wherein the processing comprises adding dummy fills to the layout patterns.
16. The system recited in claim 15 , wherein the dummy fills are added based on orientations of the layout patterns.
17. The system recited in claim 13 , wherein the processing comprises performing layout decomposition for multiple-patterning.
18. The system recited in claim 13 , wherein the pattern matching comprises fuzzy pattern matching.