Dynamic shift for test pattern compression

1. A method, executed by at least one processor of a computer, comprising:

generating compressed test patterns for a design of an integrated circuit, wherein the integrated circuit comprises:

a decompressor configurable to decompress the compressed test patterns,

a compactor configurable to compact test response data, and

scan chains coupled to outputs of the decompressor and to inputs of the compactor, each of scan chains in the circuit design being divided into a plurality of segments, and

wherein the generating comprises:

adding one or more non-shift clock cycles to one or more segments in the plurality of segments to help derive the compressed test patterns, the one or more non-shift clock cycles being additional clock cycles that the decompressor uses to generate bits for scan cells in the one or more segments of the scan chains; and

storing the compressed test patterns and information related to the added one or more non-shift clock cycles.

2. The method recited in claim 1 , wherein the one or more segments are selected from the plurality of segments based on whether a segment is compressible.

3. The method recited in claim 2 , wherein the adding comprises: determining numbers of specified bits for the plurality of segments, and the selecting of the one or more segments from the plurality of segments is further based on the numbers of specified bits.

4. The method recited in claim 3 , wherein the one or more segments are selected from the plurality of segments based further on segment locations on the scan chains.

5. The method recited in claim 1 , wherein the decompressor is a linear finite-state machine.

6. The method recited in claim 1 , wherein the adding comprises:

determining whether test compression is achievable; and

when the test compression is unachievable, adding a predetermined number of non-shift clock cycles to bits of the test patterns associated with one segment in the plurality of segments.

7. The method recited in claim 6 , wherein the adding further comprises:

determining whether the test compression is achievable after the predetermined number of non-shift clock cycles are added to bits of the test patterns associated with the one segment in the plurality of segments; and

when the test compression is unachievable, adding the predetermined number of non-shift clock cycles to bits of the test patterns associated with another segment in the plurality of segments.

8. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

generating compressed test patterns for a design of an integrated circuit, wherein the integrated circuit comprises:

a decompressor configurable to decompress the compressed test patterns,

a compactor configurable to compact test response data, and

scan chains coupled to outputs of the decompressor and to inputs of the compactor, each of scan chains in the circuit design being divided into a plurality of segments, and

wherein the generating comprises:

adding one or more non-shift clock cycles to one or more segments in the plurality of segments to help derive the compressed test patterns, the one or more non-shift clock cycles being additional clock cycles that the decompressor uses to generate bits for scan cells in the one or more segments of the scan chains; and

storing the compressed test patterns and information related to the added one or more non-shift clock cycles.

9. The one or more non-transitory computer-readable media recited in claim 8 , wherein the one or more segments are selected from the plurality of segments based on whether a segment is compressible.

10. The one or more non-transitory computer-readable media recited in claim 9 , wherein the adding comprises: determining numbers of specified bits for the plurality of segments, and the selecting of the one or more segments from the plurality of segments is further based on the numbers of specified bits.

11. The one or more non-transitory computer-readable media recited in claim 10 , wherein the one or more segments are selected from the plurality of segments based further on segment locations on the scan chains.

12. The one or more non-transitory computer-readable media recited in claim 8 , wherein the decompressor is a linear finite-state machine.

13. The one or more non-transitory computer-readable media recited in claim 8 , wherein the adding comprises:

determining whether test compression is achievable; and

when the test compression is unachievable, adding a predetermined number of non-shift clock cycles to bits of the test patterns associated with one segment in the plurality of segments.

14. The one or more non-transitory computer-readable media recited in claim 13 , wherein the adding further comprises:

determining whether the test compression is achievable after the predetermined number of non-shift clock cycles are added to bits of the test patterns associated with the one segment in the plurality of segments; and

when the test compression is unachievable, adding the predetermined number of non-shift clock cycles to bits of the test patterns associated with another segment in the plurality of segments.

15. An integrated circuit, comprising:

a decompressor configurable to decompress compressed test patterns;

a compactor configurable to compact test response data;

scan chains coupled to outputs of the decompressor and to inputs of the compactor, wherein the scan chains are divided into a plurality of segments; and

circuitry configured to add one or more non-shift clock cycles to one or more segments in the plurality of segments based on non-shift clock control data, wherein the one or more non-shift clock cycles are additional clock cycles the decompressor uses to generate bits for scan cells in the one or more segments of the scan chains.

16. The integrated circuit recited in claim 15 , wherein the decompressor is a linear finite-state machine.