Modeling substrate noise coupling for circuit simulation
View Patent ↗Aspects of the disclosed techniques relate to techniques for modeling substrate noise coupling. Electrical impedance between two contacts in the presence of one or more other contacts is modeled based on a horizontal impedance model and an L-shaped impedance model. The one or more other contacts may be clustered together in four regions first and then are represented by the horizontal impedance model and/or the L-shaped impedance model. The electrical impedance is inserted into netlist for circuit simulation.
1. A method, executed by at least one processor of a computer, comprising:
clustering two or more neighboring substrate contacts;
combining the two or more neighboring substrate contacts into one equivalent substrate contact by calculating a position for the equivalent substrate contact;
modeling electrical impedance between a first substrate contact and a second substrate contact in the presence of the equivalent substrate contact based on one of a horizontal impedance model and an L-shaped impedance model, wherein the first substrate contact, the second substrate contact and the two or more neighboring substrate contacts are substrate contacts in a layout design and/or particular areas of the layout design, and
wherein the horizontal impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of the equivalent substrate contact positioned on a line that passes through the first substrate contact and the second substrate contact, and
wherein the L-shaped impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of the equivalent substrate contact positioned on a line that passes through one of the first substrate contact and the second substrate contact and is perpendicular to a line passing through the first substrate contact and the second substrate contact;
performing circuit simulation on a circuit associated with the layout design, wherein the circuit includes a parasitic element having the electrical impedance; and
fabricating an integrated circuit based upon the layout design.
2. The method recited in claim 1 , wherein the two or more neighboring substrate contacts are located in a first quadrant, further comprising:
identifying a second quadrant comprising two or more additional neighboring substrate contacts;
combining the two or more additional neighboring substrate contacts into one additional equivalent substrate contact;
wherein the additional equivalent substrate contact is included hen modeling the electrical impedance.
3. The method recited in claim 1 , wherein the combining comprises:
clustering the two or more neighboring substrate contacts based on four quadrants centered on the first substrate contact.
4. The method recited in claim 1 , wherein the modeling comprises:
combining substrate contacts aligned in a horizontal configuration into a first equivalent substrate contact and disposed in an L-shaped configuration into a second equivalent substrate contact.
5. The method recited in claim 1 , wherein the circuit is represented by a netlist.
6. The method recited in claim 1 , wherein the position of the equivalent substrate contact is calculated using the following equations:
x
equivalent
=
x
1
*
x
2
x
1
+
x
2
θ
1
=
x
equivalent
x
2
*
θ
θ
2
=
x
equivalent
x
1
*
θ
.
7. A process for fabricating an integrated circuit comprising:
preparing a non-transitory computer-readable medium storing processor-executable instructions for causing one or more processors to perform a method, the method comprising:
clustering two or more neighboring substrate contacts;
combining the two or more neighboring substrate contacts into one equivalent substrate contact by calculating a position for the equivalent substrate contact;
modeling an electrical impedance between a first substrate contact and a second substrate contact in the presence of the equivalent substrate contact based on one of a horizontal impedance model and an L-shaped impedance model, wherein the first substrate contact, the second substrate contact and the two or more neighboring substrate contacts are substrate contacts in a layout design and/or particular areas of the layout design, and
wherein the horizontal impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of the equivalent substrate contact positioned on a line that passes through the first substrate contact and the second substrate contact, and the L-shaped impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of the equivalent substrate contact positioned on a line that passes through one of the first substrate contact and the second substrate contact and is perpendicular to a line passing through the first substrate contact and the second substrate contact; and
performing circuit simulation on a circuit associated with the layout design, wherein the circuit includes a parasitic element having the electrical impedance; and
fabricating the integrated circuit according to the layout design.
8. The process recited in claim 7 , wherein the two or mare neighboring substrate contacts are located in a first quadrant, wherein the modeling further comprises:
identifying a second quadrant comprising two or more additional neighboring substrate contacts;
combining the two or more additional neighboring substrate contacts into one additional equivalent substrate contact;
wherein the additional equivalent substrate contact is included when modeling the electrical impedance.
9. The process recited in claim 7 , wherein the combining comprises:
clustering the two or more neighboring substrate contacts based on four quadrants centered on the first substrate contact.
10. The process recited in claim 7 , wherein the modeling comprises:
combining substrate contacts aligned in a horizontal configuration into a single substrate contact and substrate contacts in the one or more substrate contacts that forms the L-shaped configuration into a single substrate contact.
11. The process recited in claim 7 , wherein the circuit is represented by a netlist.
12. The process recited in claim 7 , wherein the position of the equivalent substrate contact is calculated using the following equations:
x
equivalent
=
x
1
*
x
2
x
1
+
x
2
θ
1
=
x
equivalent
x
2
*
θ
θ
2
=
x
equivalent
x
1
*
θ
.
13. A system, comprising:
a substrate parasitics modeling unit configured to model electrical impedance between a first substrate contact and a second substrate contact in the presence of one two or more other neighboring substrate contacts based on one of a horizontal impedance model and an L-shaped impedance model, wherein the first substrate contact, the second substrate contact and the two or more neighboring substrate contacts are substrate contacts in a layout design and/or particular areas of the layout design, the horizontal impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of an equivalent substrate contact obtained by calculating a position for the equivalent substrate contact based upon positions of the two or more neighboring substrate contacts wherein the equivalent substrate contact is positioned on a line that passes through the two substrate contacts, and the L-shaped impedance model models electrical impedance for the first substrate contact and the second substrate contact in the presence of an equivalent substrate contact by calculating a position for the equivalent substrate contact based upon positions of two or more neighboring substrate contacts wherein the equivalent substrate contact is positioned on a line that passes through one of the first substrate contact and the second substrate contact and is perpendicular to a line passing through the first substrate contact and the second substrate contact; and
a simulation unit configured to perform circuit simulation on a circuit associated with the layout design, wherein the circuit includes a parasitic element having the electrical impedance; and
a fabrication facility configured for fabricating an integrated circuit according to the layout design.
14. The system recited in claim 13 , wherein the two or more neighboring substrate contacts are located in a first quadrant and wherein the substrate parasitics modeling unit comprises:
identifying a second quadrant comprising two or more additional neighboring substrate contacts; and
combining the two or more additional substrate contacts into one additional equivalent substrate contact.
15. The system recited in claim 13 , wherein the circuit is represented by a netlist.
16. The system recited in claim 13 , wherein the position of the equivalent substrate contact is calculated using the following equations:
x
equivalent
=
x
1
*
x
2
x
1
+
x
2
θ
1
=
x
equivalent
x
2
*
θ
θ
2
=
x
equivalent
x
1
*
θ
.