Reconfigurable scan network defect diagnosis
A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.
1. A method, comprising:
configuring a reconfigurable scan network in a circuit such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault, the first scan path and the second scan path sharing a same scan path segment after the programmable component;
shifting a test pattern having a length equal to a length of the second path into the reconfigurable scan network;
shifting out a part or a whole of the test pattern from the reconfigurable scan network; and
analyzing the part or the whole of the test pattern being shifted out to determine whether the programmable component has the stuck-at fault, the analyzing comprises: determining whether the part or the whole of the test pattern is shifted out at clock cycles expected for the second scan path.
2. The method recited in claim 1 , wherein the reconfigurable scan network conforms to IEEE 1687-2014 (IJTAG).
3. The method recited in claim 2 , wherein the programmable component defect suspect is a SIB or a ScanMux.
4. The method recited in claim 1 , wherein the first scan path and the second scan path are selected such that the same scan path segment after the programmable component has a shortest length.
5. The method recited in claim 1 , wherein programmable components of the reconfigurable scan network other than the programmable component defect suspect are programmed to allow a shorter scan path segment to be selected for each of the programmable components.
6. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
generating configuration data for configuring a reconfigurable scan network in a circuit such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault, the first scan path and the second scan path sharing a same scan path segment after the programmable component; and
generating a test pattern having a length equal to a length of the second path for being shifting into and out from the reconfigurable scan network configured by the configuration data, wherein a part or a whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault, the analyzing comprises: determining whether the part or the whole of the test pattern is shifted out at clock cycles expected for the second scan path.
7. The one or more non-transitory computer-readable media recited in claim 6 , wherein the reconfigurable scan network conforms to IEEE 1687-2014 (IJTAG).
8. The one or more non-transitory computer-readable media recited in claim 7 , wherein the programmable component defect suspect is a SIB or a ScanMux.
9. The one or more non-transitory computer-readable media recited in claim 6 , wherein the first scan path and the second scan path are selected such that the same scan path segment after the programmable component has a shortest length.
10. The one or more non-transitory computer-readable media recited in claim 6 , wherein programmable components of the reconfigurable scan network other than the programmable component defect suspect are programmed to allow a shorter scan path segment to be selected for each of the programmable components.
11. A method, executed by at least one processor of a computer, comprising:
generating configuration data for configuring a reconfigurable scan network in a circuit such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault, the first scan path and the second scan path sharing a same scan path segment after the programmable component; and
generating a test pattern having a length equal to a length of the second path for being shifting into and out from the reconfigurable scan network configured by the configuration data, wherein a part or a whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault, the analyzing comprises: determining whether the part or the whole of the test pattern is shifted out at clock cycles expected for the second scan path.
12. The method recited in claim 11 , wherein the reconfigurable scan network conforms to IEEE 1687-2014 (IJTAG).
13. The method recited in claim 12 , wherein the programmable component defect suspect is a SIB or a ScanMux.
14. The method recited in claim 11 , wherein the first scan path and the second scan path are selected such that the same scan path segment after the programmable component has a shortest length.
15. The method recited in claim 11 , wherein programmable components of the reconfigurable scan network other than the programmable component defect suspect are programmed to allow a shorter scan path segment to be selected for each of the programmable components.