Formal verification of booth multipliers
View Patent ↗Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output.
1. A computer-implemented formal verification method, comprising:
by a computing device,
receiving a specification of an n×n-bit multiplier circuit;
performing a direct model checking operation for a M×n-bit multiplier circuit, where M<n;
performing a series of model checking operations for multiplier circuits that are incrementally larger than the M×n-bit multiplier circuit; and
outputting a verification result of the n×n-bit multiplier circuit specification based on the direct modeling checking operation and the series of model checking operations.
2. The method of claim 1 , wherein the performing a series of model checking operations comprises, for each incrementally larger M×n-bit multiplier circuit, performing two or more separate model checking operations.
3. The method of claim 2 , wherein the two or more separate model checking operations comprise using a satisfiability-modulo-theory (“SMT”) solver and a bit-level solver.
4. The method of claim 1 , wherein the performing a direct model checking operation comprises performing a bit-level model checking operation.
5. The method of claim 1 , wherein the multiplier circuit is a Booth multiplier circuit.
6. The method of claim 1 , wherein the specification is a parameterized specification written in a hardware description language.
7. One or more non-transitory computer-readable media storing computer-executable instructions when executed by a computer cause the computer to perform a method, the method comprising:
receiving a specification of an n×n-bit multiplier circuit;
performing a direct model checking operation for a M×n-bit multiplier circuit, where M<n;
performing a series of model checking operations for multiplier circuits that are incrementally larger than the M×n-bit multiplier circuit; and
outputting a verification result of the n×n-bit multiplier circuit specification based on the direct modeling checking operation and the series of model checking operations.
8. The one or more non-transitory computer-readable media of claim 7 , wherein the performing a series of model checking operations comprises, for each incrementally larger M×n-bit multiplier circuit, performing two or more separate model checking operations.
9. The one or more non-transitory computer-readable media of claim 8 , wherein the two or more separate model checking operations comprise using a satisfiability-modulo-theory (“SMT”) solver and a bit-level solver.
10. The one or more non-transitory computer-readable media of claim 7 , wherein the performing a direct model checking operation comprises performing a bit-level model checking operation.
11. The one or more non-transitory computer-readable media of claim 7 , wherein the multiplier circuit is a Booth multiplier circuit.
12. The one or more non-transitory computer-readable media of claim 7 , wherein the specification is a parameterized specification written in a hardware description language.
13. One or more non-transitory computer-readable media storing computer-executable instructions when executed by a computer cause the computer to perform a method, the method comprising:
receiving a specification of a Booth multiplier circuit;
performing an initial model checking operation for a smaller version of the Booth multiplier circuit;
performing a series of subsequent model checking operations for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and
outputting a verification result of the Booth multiplier circuit.
14. The one or more non-transitory computer-readable media of claim 13 , wherein the initial model checking operation is performed by a bit-level solver.
15. The one or more non-transitory computer-readable media of claim 13 , wherein the initial model checking operation comprises performing model checking for an M×n-bit Booth multiplier circuit, where M is less than 5.
16. The one or more non-transitory computer-readable media of claim 15 , wherein, for each incrementally larger Booth multiplier circuit, M is incremented by 1.
17. The one or more non-transitory computer-readable media of claim 13 , wherein a first of the two or more model checking operations comprises model checking between two behavioral multipliers and a second of the two or more model checking operations comprises model checking between two Booth multipliers.
18. The one or more non-transitory computer-readable media of claim 17 , wherein the first of the two or more model checking operations is performed by a SMT solver and the second of the two or more model checking operations is performed by a bit-level solver.
19. The one or more non-transitory computer-readable media of claim 13 , wherein the specification is a parameterized specification written in a hardware description language.