IP Library › Granted Patent US 8,953,400
Granted Patent B2
US 8,953,400 · App. 13/628,481 · Granted Feb 10, 2015

Data control circuit

Inventor: Sang Kwon Lee (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
G11C7/1048
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Quick Facts
Patent No.
US 8,953,400
App. No.
13/628,481
Granted
Feb 10, 2015
Kind
B2
Abstract

The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation.

Claims (46)

1. A data control circuit comprising:

a first input/output line precharging circuit configured to precharge a first global input/output line at a level of an internal voltage generated internally when reading or writing operations are inoperative;

a second input/output line precharging circuit configured to precharge a second global input/output line at the level of an internal voltage generated internally when the reading or writing operations are inoperative; and

a repeater configured to amplify and transfer data of the first global input/output line to the second global input/output line during the reading operation and configured to amplify and transfer data of the second global input/output line to the first global input/output line during the writing operation, wherein the repeater generates first pull-up and pull-down signals from a signal of the first global input/output line in response to a first enable signal that is activated in the reading operation, and second pull-up and pull-down signals from a signal of the second global input/output line in response to a second enable signal that is activated in the writing operation, wherein the first input/output line precharging circuit comprises a first drive signal generator configured to generate a first drive signal that is disabled when either the first enable signal or the second enable signal is enabled.

2. The data control circuit according to claim 1 , wherein the first input/output line precharging circuit further comprises:

a first driving element configured to drive the first global input/output line at an internal voltage when the first drive signal is enabled.

3. The data control circuit according to claim 2 , wherein the second input/output line precharging circuit comprises:

a second drive signal generator configured to generate a second drive signal in response to receiving the first and second enable signals; and

a second driving element configured to drive the second global input/output line at the internal voltage in response to the second drive signal.

4. The data control circuit according to claim 3 , wherein the repeater comprises:

a first driving circuit that comprises a first pull-up element configured to pull up a signal of the second global input/output line in response to the first pull-up signal and comprises a first pull-down element configured to pull down a signal of the second global input/output line in response to the first pull-down signal; and

a second driving circuit that comprises a second pull-up element configured to pull up a signal of the first global input/output line in response to the second pull-up signal and the second driving circuit comprises a second pull-down element configured to pull down a signal of the first global input/output line in response to the second pull-down signal.

5. The data control circuit according to claim 4 , wherein the first pull-up element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the first pull-down element, wherein the second pull-up element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the second pull-down element.

6. The data control circuit according to claim 1 , wherein the first input/output line precharging circuit comprises:

a first drive signal generator configured to generate a first drive signal in response to receiving the first enable signal-and configured to generate the first drive signal in response to receiving the second enable signal; and

a first driving element configured to precharge the first global input/output line to a ground voltage in response to the first drive signal.

7. The data control circuit according to claim 6 , wherein the second input/output line precharging circuit comprises:

a second drive signal generator configured to generate a second drive signal in response to receiving the first and second enable signals; and

a second driving element configured to precharge the second global input/output line to the ground voltage in response to the second drive signal.

8. The data control circuit according to claim 7 , wherein the repeater comprises:

a first driving circuit that comprises a first pull-up element configured to pull up a signal of the second global input/output line in response to the first pull-up signal and comprises a first pull-down element configured to pull down a signal of the second global input/output line in response to the first pull-down signal;and

a second driving circuit that comprises a second pull-up element configured to pull up a signal of the first global input/output line in response to the second pull-up signal and the second driving circuit comprises a second pull-down element configured to pull down a signal of the first global input/output line in response to the second pull-down signal.

9. The data control circuit according to claim 8 , wherein the first pull-down element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the first pull-up element, wherein the second pull-down element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the second pull-up element.

10. A data control circuit comprising:

an input/output line precharging circuit configured to precharge first and second global input/output lines at a level of an internal voltage generated internally when either reading or writing operations are inoperative;

a first driver configured to drive the first global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation;

a repeater configured to amplify and transfer data of the first global input/output line to the second global input/output line in the reading operation and configured to amplify and transfer data of the second global input/output line to the first global input/output line in the writing operation; and

a second driver configured to drive the second global input/output line in response to receiving data from a data pad during the writing operation, wherein the repeater generates first pull-up and pull-down signals from a signal of the first global input/output line in response to a first enable signal that is activated in the reading operation, and second pull-up and pull-down signals from a signal of the second global input/output line in response to a second enable signal that is activated in the writing operation, wherein the input/output line precharging circuit comprises a first drive signal generator configured to generate a first drive signal that is disabled when either the first enable signal or the second enable signal is enabled.

11. The data control circuit according to claim 10 , wherein the input/output line precharging circuit further comprises:

a driving element configured to precharge the first global input/output line at an internal voltage or a ground voltage when the first drive signal is enabled.

12. The data control circuit according to claim 10 , wherein the input/output line precharging circuit further comprises:

a second drive signal generator configured to generate a second drive signal that is disabled when the first enable signal or the second enable signal is enabled; and

a second driving element configured to precharge the second global input/output line at the internal voltage or a ground voltage when the second drive signal is enabled.

13. The data control circuit according to claim 10 , wherein the repeater comprises:

a first driving circuit that comprises a first pull-up element configured to pull up a signal of the second global input/output line in response to the first pull-up signal and comprises a first pull-down element configured to pull down a signal of the second global input/output line in response to the first pull-down signal; and

a second driving circuit that comprises a second pull-up element configured to pull up a signal of the first global input/output line in response to the second pull-up signal and comprises a second pull-down element configured to pull down a signal of the first global input/output line in response to the second pull-down signal.

14. The data control circuit according to claim 13 , wherein, when the first and second global input/output lines are driven at an internal voltage by the first and second input/output line precharging circuits, the first pull-up element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the first pull-down element and the second pull-up element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the second pull-down element.

15. The data control circuit according to claim 13 , wherein, when the first and second global input/output lines are driven at a ground voltage by the first and second input/output line precharging circuits, the first pull-down element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the first pull-up element and the second pull-down element comprises a MOS transistor configured to have a threshold voltage lower than a threshold voltage of the second pull-up element.

16. The data control circuit according to claim 10 , wherein the first driver comprises:

a differential amplifier configured to generate pull-up and pull-down signals by differentially amplifying data of the local input/output line and the complementary local input/output line; and

a driving circuit configured to drive the first global input/output line in response to receiving the pull-up and pull-down signals,

wherein the driving circuit comprises a MOS transistor having a threshold voltage lower than threshold voltages of MOS transistors included in the differential amplifier.

17. The data control circuit according to claim 10 , wherein the second driver comprises:

a differential amplifier configured to generate pull-up and pull-down signals by differentially amplifying the data of the data pad; and

a driving circuit configured to drive the second global input/output line in response to receiving the pull-up and pull-down signals,

wherein the driving circuit comprises a MOS transistor having a threshold voltage lower than threshold voltages of MOS transistors included in the differential amplifier.

Assignments (1)
CHANGE OF NAME Recorded Jan 30, 2013
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 029720/0390 →
Priority Claims (1)
KR 10-2009-0070761 · Jul 31, 2009 · national
Continuity (2)
Division 12649475 · Dec 30, 2009
Related Publication 20130033949A1 · Feb 7, 2013