Contact structure of semiconductor device
The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.
1. A contact structure for a semiconductor device comprising:
a substrate comprising a major surface and a trench below the major surface;
a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, the strained material having a topmost surface and a bottommost surface and being of substantially uniform composition from the topmost surface to the bottommost surface;
an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a bottom comprising the topmost surface of the strained material;
a metal oxide layer coating the sidewalls and bottom of the opening, wherein the metal oxide layer has a thickness ranging from 1 nm to 10 nm; and
a metal layer filling a coated opening of the metal oxide layer.
2. The contact structure of claim 1 , wherein the strained material comprises Si, Ge, SiGe, SiC, SiP, or III-V semiconductor material.
3. The contact structure of claim 1 , wherein the strained material filling the trench extends upward over the major surface.
4. The contact structure of claim 1 , wherein the metal oxide layer comprises a material selected from the group consisting of TiO, TiO 2 , Ti 2 O 3 , and combinations thereof.
5. The contact structure of claim 1 , wherein the metal layer comprises Ta, Ti, Hf, Zr, Ni, W, Co, Cu, or Al.
6. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a substrate comprising a major surface;
a gate stack on the major surface of the substrate;
a trench below the major surface adjacent to the gate stack;
a shallow trench isolations (STI) region disposed on a side of the trench opposite the gate stack, wherein the STI region is within the substrate;
a semiconductive strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a bottom comprising the semiconductive strained material;
a metal oxide layer coating the sidewalls and bottom of the opening, wherein the metal oxide layer has a thickness ranging from 1 nm to 10 nm; and
a metal layer filling a coated opening of the dielectric layer.
7. The MOSFET of claim 6 , wherein the strained material comprises Si, Ge, SiGe, SiC, SiP, or III-V semiconductor material.
8. The MOSFET of claim 6 , wherein the strained material filling the trench extends upward over the major surface.
9. The MOSFET of claim 6 , wherein the metal oxide layer comprises TiO, TiO 2 , or Ti 2 O 3 .
10. The MOSFET of claim 6 , wherein the metal layer comprises Ta, Ti, Hf, Zr, Ni, W, Co, Cu, or Al.
11. A contact structure for a semiconductor device comprising:
a silicon substrate comprising a major surface and a trench below the major surface;
a strained material comprising germanium filling the trench, the strained material having a topmost surface and a bottommost surface and being of substantially uniform composition from the topmost surface to the bottommost surface;
an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a bottom comprising the topmost surface of the strained material;
a metal oxide layer coating the sidewalls and bottom of the opening, wherein the metal oxide layer has a thickness ranging from 1 nm to 10 nm; and
a metal layer filling a coated opening of the metal oxide layer.
12. The contact structure of claim 11 , wherein the strained material also comprises silicon.
13. The contact structure of claim 11 , wherein the strained material filling the trench extends upward over the major surface.
14. The contact structure of claim 11 wherein the ILD comprises silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide and/or combinations thereof.
15. The contact structure of claim 11 , wherein the metal oxide layer comprises a material selected from the group consisting of TiO, TiO 2 , Ti 2 O 3 , and combinations thereof.
16. The contact structure of claim 11 , wherein the metal layer comprises Ta, Ti, Hf, Zr, Ni, W, Co, Cu, or Al.
17. The contact structure of claim 11 further comprising a gate stack on the major surface of the substrate.
18. The contact structure of claim 17 further comprising a sidewall spacer on a side of the gate stack.
19. The contact structure of claim 18 wherein the trench is aligned to the sidewall spacer.