METHOD FOR RADIATION HARDENING AN INTEGRATED CIRCUIT
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
1 . A method for manufacturing an integrated circuit product having an existing layout design, to reduce the effects of radiation on said integrated circuit product, said method comprising:
providing a semiconductor body having a lightly-doped region of a first conductivity type proximate to a top surface of the body, and having a conductive bottom surface;
forming device wells of both the first conductivity type and a second conductivity type opposite the first conductivity type within the lightly doped region, generally in accordance with said existing layout design, said device wells extending to the surface of the body and to a certain depth within the semiconductor body;
forming transistors within said device wells of the first conductivity type and the second conductivity type, generally in accordance with said existing layout design;
forming a heavily-doped buried layer at a depth within the semiconductor body greater than the certain depth, said heavily-doped buried layer extending continuously beneath the device wells, and providing a conductive path between the heavily-doped buried layer and the conductive bottom surface of the semiconductor body; then
forming electrical interconnections coupled to the transistors, generally in accordance with said existing layout design; and
providing an electrical connection to the conductive bottom surface of the semiconductor body.