IP Library Granted Patent US 10,014,068
Granted Patent B2
US 10,014,068 · App. 13/632,564 · Granted Jul 3, 2018

Semiconductor device

Inventors: Masayuki Sakakura (Isehara, JP); Yuugo Goto (Isehara, JP); Hiroyuki Miyake (Atsugi, JP); Daisuke Kurosaki (Tochigi, JP)
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
G11C19/184H01L27/124H01L27/1222H01L27/1225G09G2310/0275G09G2310/0286H01L27/0248
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Quick Facts
Patent No.
US 10,014,068
App. No.
13/632,564
Granted
Jul 3, 2018
Kind
B2
Abstract

A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.

Claims (104)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein:

the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor have a same conductivity type;

one of a source and a drain of the first transistor is electrically connected to a first wiring;

the other of the source and the drain of the first transistor is electrically connected to a second wiring;

one of a source and a drain of the second transistor is electrically connected to the second wiring;

the other of the source and the drain of the second transistor is electrically connected to a third wiring;

one of a source and a drain of the third transistor is electrically connected to a fourth wiring;

the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;

one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;

the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;

a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;

the first conductive layer is configured to be the gate of the first transistor;

the third conductive layer is configured to be a gate of the third transistor; and

the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor.

2. The semiconductor device according to claim 1 , wherein:

the second conductive layer and a fourth conductive layer are provided in a same layer; and

the fourth conductive layer is configured to be the one of the source and the drain of the first transistor.

3. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein:

the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor have a same conductivity type;

one of a source and a drain of the first transistor is electrically connected to a first wiring;

the other of the source and the drain of the first transistor is electrically connected to a second wiring;

one of a source and a drain of the second transistor is electrically connected to the second wiring;

the other of the source and the drain of the second transistor is electrically connected to a third wiring;

one of a source and a drain of the third transistor is electrically connected to a fourth wiring;

the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;

one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;

the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;

a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;

the first conductive layer is configured to be the gate of the first transistor;

the third conductive layer is configured to be a gate of the third transistor;

the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor; and

a ratio of a channel width of the first transistor to a channel length of the first transistor is larger than a ratio of a channel width of the third transistor to a channel length of the third transistor.

4. The semiconductor device according to claim 3 , wherein;

the second conductive layer and a fourth conductive layer are provided in a same layer; and

the fourth conductive layer is configured to be the one of the source and the drain of the first transistor.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein:

the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor have a same conductivity type;

one of a source and a drain of the first transistor is electrically connected to a first wiring;

the other of the source and the drain of the first transistor is electrically connected to a second wiring;

one of a source and a drain of the second transistor is electrically connected to the second wiring;

the other of the source and the drain of the second transistor is electrically connected to a third wiring;

one of a source and a drain of the third transistor is electrically connected to a fourth wiring;

the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;

one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;

the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;

a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;

the first conductive layer is configured to be the gate of the first transistor;

the third conductive layer is configured to be a gate of the third transistor;

the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor; and

the first conductive layer is constantly electrically connected to the third conductive layer.

6. The semiconductor device according to claim 5 , wherein:

the second conductive layer and a fourth conductive layer are provided in a same layer; and

the fourth conductive layer is configured to be the one of the source and the drain of the first transistor.

7. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein:

the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor have a same conductivity type;

one of a source and a drain of the first transistor is electrically connected to a first wiring;

the other of the source and the drain of the first transistor is electrically connected to a second wiring;

one of a source and a drain of the second transistor is electrically connected to the second wiring;

the other of the source and the drain of the second transistor is electrically connected to a third wiring;

one of a source and a drain of the third transistor is electrically connected to a fourth wiring;

the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;

one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;

the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;

one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;

the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;

a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;

a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;

the first conductive layer is configured to be the gate of the first transistor;

the third conductive layer is configured to be a gate of the third transistor;

the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor; and

a ratio of a channel width of the first transistor to a channel length of the first transistor is larger than a ratio of a channel width of the third transistor to a channel length of the third transistor.

8. The semiconductor device according to claim 7 , wherein:

the second conductive layer and a fourth conductive layer are provided in a same layer; and

the fourth conductive layer is configured to be the one of the source and the drain of the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2013
From: SAKAKURA, MASAYUKI; GOTO, YUUGO; MIYAKE, HIROYUKI; KUROSAKI, DAISUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 029558/0875 →
Priority Claims (1)
JP 2011-222990 · Oct 7, 2011 · national
Continuity (1)
Related Publication 20130088468A1 · Apr 11, 2013
Cited By (3)
US 12,243,459 US 12,431,207 US 12,706,013