Field effect transistor with source, heavy body region and shielded gate
A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
1. A MOSFET, comprising:
a trench having a lower portion and an upper portion, the trench being disposed in a semiconductor region;
a shield electrode disposed in the lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric, the shield electrode having a curved bottom surface;
a gate electrode disposed in the upper portion of the trench, the gate electrode being over but insulated from the shield electrode, the lower portion of the trench having a width narrower than a width of the upper portion of the trench, at least a portion of a top surface of the gate electrode having a slope non-parallel to a bottom surface of the gate electrode; and
an inter-poly dielectric disposed between the shield electrode and the gate electrode,
the semiconductor region, which defines at least a portion of a mesa, including:
a substrate of a first conductivity type,
a first silicon region of a second conductivity type over the substrate, the first silicon region having a first portion extending to a depth intermediate a top surface and a bottom surface of the gate electrode, the first silicon region having a second portion extending to a depth intermediate a top surface and a bottom surface of the shield electrode,
a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region, and
a source region of the first conductivity type in the first silicon region, the source region being adjacent the upper trench portion.
2. The MOSFET of claim 1 wherein the first portion of the first silicon region includes a vertically-extending channel region defined by a spacing between the source region and the second silicon region.
3. The MOSFET of claim 1 further comprising:
a heavy body region of the second conductivity type in the first silicon region; and
a source interconnect layer electrically contacting the source region and the heavy body region but being insulated from the gate electrode.
4. An apparatus, comprising:
a first trench disposed in a silicon region of a first conductivity type;
a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric, the shield electrode having a curved bottom surface;
a gate electrode disposed in the first trench above the shield electrode, a portion of the first trench disposed around the shield electrode having a width narrower than a width of a portion of the first trench disposed around the gate electrode, the shield electrode having a width less than a width of the gate electrode, at least a portion of a top surface of the gate electrode having a slope non-parallel to a bottom surface of the gate electrode;
an inter-poly dielectric disposed between the shield electrode and the gate electrode;
a second trench disposed in the silicon region;
a mesa disposed between the first trench and the second trench, the mesa having a recessed portion; and
a region of a second conductivity type disposed in the mesa and disposed above the silicon region of the first conductivity type, the region of the second conductivity type having a depth lower than a depth of at least a portion of the bottom surface of the gate electrode.
5. The apparatus of claim 4 , wherein the first trench extends into and terminates within an epitaxial layer.
6. The apparatus of claim 4 , wherein at least a portion of the first trench has a tapered shape.
7. The apparatus of claim 4 , wherein at least a portion of the top surface of the gate electrode has a V-shape.
8. The apparatus of claim 4 , further comprising:
a gate dielectric formed along a sidewall of an upper portion of the first trench, the gate dielectric having a thickness less than a thickness of the inter-poly dielectric.
9. The apparatus of claim 4 , wherein the gate electrode has a top surface at a depth that is recessed relative to a top surface of the mesa.
10. The apparatus of claim 4 , wherein the gate electrode has a top surface at a depth that is recessed relative to a top of the trench.
11. A field effect transistor (FET), comprising:
a first trench disposed in a silicon region of a first conductivity type, at least a portion of the first trench has a tapered shape;
a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric, the shield electrode having a curved bottom surface;
a gate electrode disposed in the first trench above the shield electrode, a portion of the first trench disposed around the shield electrode having a width narrower than a width of a portion of the first trench disposed around the gate electrode, at least a portion of a top surface of the gate electrode has a slope non-parallel to a bottom surface of the gate electrode;
an inter-poly dielectric disposed between the shield electrode and the gate electrode;
a second trench disposed in the silicon region;
a mesa disposed between the first trench and the second trench and having a recessed portion, the recessed portion of the mesa having the bottom surface lower than at least a portion of a top surface of the gate electrode;
a region of a second conductivity type disposed in the mesa and disposed above the silicon region of the first conductivity type; and
a gate dielectric formed along a sidewall of an upper portion of the first trench, the gate dielectric having a thickness less than a thickness of the inter-poly dielectric.
12. The FET of claim 11 , wherein the region of the second conductivity type has a depth lower than a depth of at least a portion of a bottom surface of the gate electrode.
13. The FET of claim 11 , wherein the first trench extends into and terminates within an epitaxial layer.
14. The FET of claim 11 , wherein the shield electrode has a width that is less than a width of the gate electrode.
15. The FET of claim 11 , wherein the gate electrode has a top surface, at least a portion of the top surface of the gate electrode has a V-shape.
16. An apparatus, comprising:
a first trench disposed in a silicon region, at least a portion of the first trench having a tapered shape;
a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric;
a gate electrode disposed in the first trench above the shield electrode, a portion of the first trench disposed around the shield electrode having a width narrower than a width of a portion of the first trench disposed around the gate electrode, at least a portion of a top surface of the gate electrode having a V-shape;
an inter-poly dielectric disposed between the shield electrode and the gate electrode;
a second trench disposed in the silicon region;
a mesa disposed between the first trench and the second trench and having a recessed portion; and
a gate dielectric formed along a sidewall of an upper portion of the first trench, the gate dielectric having a thickness less than a thickness of the inter-poly dielectric.
17. The apparatus of claim 16 , wherein the silicon region has a first conductivity type,
the apparatus further comprising:
a region of a second conductivity type disposed in the mesa and disposed above the silicon region of the first conductivity type.
18. The apparatus of claim 16 , wherein the shield electrode has a width that is less than a width of the gate electrode.
19. The apparatus of claim 16 , wherein the gate electrode has a top surface at a depth that is recessed relative to a top of the trench.
20. The apparatus of claim 16 , wherein the first trench extends into and terminates within an epitaxial layer.