Method for providing data protection for data stored within a memory element and integrated circuit device therefor
View Patent ↗A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.
1. A method for providing data protection for data stored within a Random Access Memory element, the method comprising:
receiving data to be written to memory;
dividing the received data into a plurality of n data sections, wherein each one of the n data sections comprises at least one data bit;
applying an error correction code to each one of the n data sections to form a respective codeword section, wherein each codeword section comprises the at least one data bit and at least one Error Correction Code (ECC) bit appended to the at least one data bit;
interleaving every data bit and every ECC bit of each codeword section with every data bit and every ECC bit of every other codeword section to form an interleaved data codeword, wherein consecutive bits of each codeword section are located at one in every n consecutive bits of the interleaved data codeword; and
writing within a single clock cycle the interleaved data codeword to memory.
2. The method of claim 1 further comprising:
multiplexing, prior to said writing, the interleaved data codeword, wherein consecutive bits of the interleaved data codeword are written within the single clock cycle to one in every i consecutive bit cells in a row of memory bit cells of the memory.
3. The method of claim 1 further comprising:
multiplexing, prior to said writing, the interleaved data codeword, wherein consecutive bits of the interleaved data codeword are written within the single clock cycle to one in every four consecutive bit cells in a row of memory bit cells of the memory.
4. The method of claim 1 further comprising:
applying a single-bit error correction code to each one of the n data sections to form the respective codeword section.
5. The method of claim 1 further comprising:
dividing the received data into two data sections.
6. A method for providing data protection for data stored within a Random Access Memory element, the method comprising:
reading, in a single clock cycle, a data codeword from a memory;
de-interleaving the read data codeword to obtain a plurality of n codeword sections, wherein consecutive bits of each codeword section are obtained from one in every n consecutive bits of the read data codeword and each codeword section comprises at least one data bit and at least one Error Correction Code (ECC) bit appended to the at least one data bit;
performing error detection and correction on each one of the n codeword sections to retrieve a respective data section; and
combining each one of the n retrieved respective data sections to reproduce user data.
7. The method of claim 6 further comprising:
de-multiplexing, prior to said de-interleaving, the read data codeword, wherein consecutive bits of the data codeword are from one in every i consecutive bit cells in a row of memory bit cells of the memory.
8. The method of claim 6 further comprising:
de-multiplexing, prior to said de-interleaving, the read data codeword, wherein consecutive bits of the data codeword are from one in every four consecutive bit cells in a row of memory bit cells of the memory.
9. The method of claim 6 further comprising:
performing single-bit error detection and correction on each one of the n de-interleaved codeword sections to retrieve the respective data section.
10. The method of claim 6 further comprising:
de-interleaving the read data codeword to obtain two codeword sections.
11. The method of claim 6 further comprising:
reading a 44 bit data codeword from the memory;
de-interleaving the 44 bit data codeword to obtain two 22 bit data codeword sections;
performing error detection and correction on the de-interleaved data codeword sections to retrieve two 16 bit data sections; and
combining the two 16 bit data sections to reproduce a 32 bit data word.
12. An integrated circuit device comprising a memory access module for writing received data to a Random Access Memory, wherein the memory access module comprises:
a plurality of n error correcting code blocks, each coupled to receive one of n sections of the received data, and configured to apply an error correction code to each one of the n received data sections to form a respective codeword section, wherein each one of the n data sections comprises at least one data bit, and the respective codeword section comprises the at least one data bit and at least one Error Correction Code (ECC) bit appended to the at least one data bit;
wherein the memo access module is configured to:
interleave every data bit and every ECC bit of each one of the respective code word sections with every data bit and every ECC bit of every other code word section to form an interleaved data codeword, wherein consecutive bits of each codeword section are located at one in every n consecutive bits of the interleaved data codeword; and
write in a single clock cycle the interleaved data codeword to the Random Access Memory.
13. The integrated circuit device of claim 12 , further comprising a multiplexer, coupled to the plurality of n error correcting code blocks, configured to write consecutive bits of the interleaved data codeword to one in every i consecutive bit cells in a row of memory bit cells of the Random Access Memory.
14. The integrated circuit device of claim 12 , further comprising a multiplexer, coupled to the plurality of n error correcting code blocks, configured to write consecutive bits of the interleaved data codeword to one in every four consecutive bit cells in a row of memory bit cells of the Random Access Memory.
15. The integrated circuit device of claim 12 , further configured to apply a single-bit error correction code to each one of the n received data sections to form the respective codeword section.
16. The integrated circuit device of claim 12 , further configured to divide the received data into two data sections.
17. The integrated circuit device of claim 12 , further configured to:
read, in the single clock cycle, a data codeword from the Random Access Memory;
de-interleave the read data codeword to obtain the n codeword sections;
perform error detection and correction on each one of the n codeword sections to retrieve the respective data section; and
combine each one of the n retrieved respective data sections to reproduce user data.
18. The integrated circuit device of claim 17 , further comprising a multiplexer configured to read consecutive bits of the data codeword from one in every i consecutive bit cells in a row of memory bit cells of the memory.
19. The integrated circuit device of claim 17 , further comprising a multiplexer configured to read consecutive bits of the data codeword from one in every four consecutive bit cells in a row of memory bit cells of the memory.
20. The integrated circuit device of claim 17 , further configured to perform single-bit error detection and correction on each one of the n codeword sections to retrieve the respective data section.