IP Library Granted Patent US 9,161,438
Granted Patent B2
US 9,161,438 · App. 13/638,518 · Granted Oct 13, 2015

Stress buffer layer and method for producing same

Inventor: Hidetoshi Masuda (Tokyo, JP)
Assignee: TAIYO YUDEN CO., LTD.
H05K1/0271H01R43/007H05K1/03H05K1/0306H05K1/18H05K3/32H05K3/3431H01R13/2414H05K2201/10378H05K2201/10636H05K2201/10674H05K2201/10962
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Quick Facts
Patent No.
US 9,161,438
App. No.
13/638,518
Granted
Oct 13, 2015
Kind
B2
Abstract

A stress buffer sheet 10 is constituted by arranging external conductive layers 16 A and 16 B on the front and rear main surfaces of a through electrode layer 13 . Columnar internal electrodes 14 are formed using a porous oxide base material 30 formed by anodic oxidation of valve metal; the oxide base material 30 is selectively removed after the internal electrodes 14 have been formed, and a resin 12 is filled in a resultant void space. The resin 12 has a small Young's modulus and can be deformed together with the internal electrode 14 . In a structure having a wiring board 20 and an electronic component 24 connected through the stress buffer sheet 10 , when stress acts on the joint portion during mounting of the electronic component 24 , the whole of the through electrode layer 13 is deformed so that the stress is absorbed or released.

Claims (5)

1. A stress buffer layer comprising:

a plate-like base material made of an anodic oxide of a valve metal that has been subject to anodic oxidation, the base material having a top surface and a bottom surface each covered by a pair of insulating material layers made of an insulating material having a Young's modulus smaller than the anodic oxide of the valve metal, the base material having many through holes penetrating through the top surface and the bottom surface which are formed during the anodic oxidation of the valve metal; and

an internal electrode filled in the many through holes and conductively connected directly or indirectly to an electronic component, wherein both ends of the internal electrode are formed so as to be substantially on the same plane as the top and bottom surfaces of the base material at a point in time immediately before the internal electrode is connected to the electronic component.

2. The stress buffer layer according to claim 1 , wherein the insulating material is resin.

3. The stress buffer layer according to claim 1 , further comprising an external conductive layer arranged on at least one of the top surface and the bottom surface of the plate-like base material and conductively connected to at least one of the many internal electrodes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2025
From: TAIYO YUDEN CO., LTD.
To: AIST SOLUTIONS CO.
Reel/Frame 073304/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2012
From: MASUDA, HIDETOSHI
To: TAIYO YUDEN CO., LTD.
Reel/Frame 029466/0481 →
Priority Claims (1)
JP 2010-082313 · Mar 31, 2010 · national
Continuity (1)
Related Publication 20130092424A1 · Apr 18, 2013