Transistor with high electron mobility and inhomogeneous layer resistance of the guide channel
For an HEMT component, in particular on the basis of GaN, it is proposed, for the purpose of reducing field spikes in the conduction channel, in a partial section of the conduction channel between gate electrode and drain electrode, to set the sheet resistance of the conduction channel such that it is higher than in adjacent regions. Various measures for subsequently increasing the sheet resistance in an area-selective manner are specified.
1. Semiconductor component in the form of an HEMT, with a first semiconductor layer and a second deposited over the latter, and a two-dimensional electron gas that forms in the first semiconductor layer, at the layer boundary to the second semiconductor layer, in a conduction channel, as well as with a source electrode and a drain electrode disposed laterally at a distance from one another, connected with the conduction channel in electrically conductive manner, and a gate electrode disposed between these, wherein the sheet resistance of the conduction channel is inhomogeneous in the current direction between source electrode and drain electrode, in such a manner that in a partial section of the conduction channel that lies between gate electrode and drain electrode, the sheet resistance of the conduction channel is elevated as compared with adjacent regions of the conduction channel that lie on both sides of the partial section, wherein the partial section is shorter than the expanse of the conduction channel between gate electrode and drain electrode.
2. Component according to claim 1 , wherein the sheet resistance in the partial section is higher, by at least 4%, particularly by at least 8%, than the average sheet resistance in the adjacent regions.
3. Component according to claim 1 , wherein the sheet resistance assumes a minimal value, within the progression between source electrode and drain electrode, in the region that lies adjacent in the direction toward the source electrode.
4. Component according to claim 1 , wherein the partial section amounts to less than 60%, particularly less than 40% of the expanse of the conduction channel between gate electrode and drain electrode.
5. Component according to claim 1 , wherein the length of the partial section amounts to at least 10%, particularly at least 20% of the expanse of the conduction channel between gate electrode and drain electrode.
6. Component according to claim 1 , wherein the partial section lies closer to the gate electrode than to the drain electrode.
7. Component according to claim 1 , wherein the partial section overlaps with the position of the gate electrode.
8. Component according to claim 1 , wherein the second semiconductor layer has a lesser layer thickness above the partial section than above the adjacent regions.
9. Component according to claim 8 , wherein the layer thickness of the second semiconductor layer is less by at least 5%, particularly by at least 10%, above the partial section than above the adjacent regions.
10. Component according to claim 8 , wherein the region of the reduced layer thickness is disposed laterally offset relative to the gate electrode, in the direction of the drain electrode.
11. Component according to claim 1 , wherein the maximal layer thickness of the second semiconductor layer between source electrode and drain electrode amounts to less than 30 nm, particularly less than 25 nm.
12. Component according to claim 1 , wherein the second semiconductor layer contains additional components, introduced into it by means of ion implantation after deposition of the second semiconductor layer, above the partial section.
13. Component according to claim 12 , wherein the second semiconductor layer has lattice damage caused by the ion implantation, above the partial section.
14. Component according to claim 12 , wherein ions of the elements O, H, Ar, N, and/or Zn are introduced by means of ion implantation, as additional components.
15. Component according to claim 1 , wherein a further semiconductor layer is deposited above the second semiconductor layer, as the uppermost semiconductor layer.
16. Component according to claim 15 , wherein the further semiconductor layer is not present above the partial section.
17. Component according to claim 1 , wherein a dielectric layer is deposited onto an uppermost semiconductor layer, as a passivation layer.
18. Component according to claim 17 , wherein the passivation layer is different above the partial section, in terms of composition and/or parameters of the deposition process, from the passivation layer above the adjacent regions.
19. Component according to claim 18 , wherein the passivation layer contains an additional component above the partial section, as compared with the passivation layer above the adjacent regions.
20. Component according to claim 17 , wherein the passivation layer is formed, at least predominantly, from silicon nitride.
21. Component according to claim 20 , wherein the passivation layer contains at least one of the elements O, Ar above the partial section.
22. Component according to claim 1 , wherein the first semiconductor layer consists of GaN.
23. Component according to claim 22 , wherein the second semiconductor layer consists of Al x Ga 1-x N.
24. Component according to claim 23 , wherein the Al component x amounts to at most x=0.3, particularly at most x=0.25.
25. Component according to claim 1 , wherein the second semiconductor layer is undoped.