Substrate assembly for crystal growth and fabricating method for light emitting device using the same
View Patent ↗A substrate assembly on which a first conduction-type semiconductor layer, an active layer and a second conduction-type semiconductor layer are formed is disclosed, the substrate assembly comprising a first substrate, a second substrate and a bonding layer interposed there between. In the substrate assembly, the thermal expansion coefficient of the bonding layer is smaller than or equal to that of at least one of the first and second substrates.
1. A substrate assembly, comprising:
a first substrate;
a second substrate; and
a bonding layer completely filling the area between the first substrate and the second substrate,
wherein the thermal expansion coefficient of the bonding layer is smaller than or equal to that of at least one of the first substrate and the second substrate,
wherein the first and second substrate physically contact the bonding layer, and
wherein sides of the first and second substrates facing each other have the same surface area.
2. The substrate assembly of claim 1 , wherein the first substrate and the second substrate are homogeneous.
3. The substrate assembly of claim 2 , wherein the first substrate and the second substrate comprise sapphire.
4. The substrate assembly of claim 1 , wherein the bonding layer comprises at least one of a nitride semiconductor, a silicon oxide (SiO x ), a silicon nitride (SiN x ), a mixture thereof, and a metal comprising Ti, Cr, Ni, Cu, W, Au, Ag, or an alloy thereof.
5. The substrate assembly of claim 4 , wherein the bonding layer is formed on a first surface of at least one of the first substrate and the second substrate using plasma enhanced chemical vapor deposition, sputtering, or plating.
6. A method of forming a light emitting device, the method comprising:
forming a bonding layer on at least one of a first substrate and a second substrate;
bonding the first substrate and the second substrate to each other, the bonding layer being interposed between the first substrate and the second substrate;
forming at least one semiconductor lamination structure on the first substrate;
removing the bonding layer and the second substrate after the formation of the at least one semiconductor lamination structure; and
grinding the first substrate,
wherein sides of the first and second substrates facing each other have the same surface area.
7. The method of claim 6 , wherein the first substrate and the second substrate are homogeneous.
8. The method of claim 7 , wherein the first substrate and the second substrate comprise sapphire.
9. The method of claim 6 , wherein the bonding layer comprises at least one of a nitride semiconductor, a silicon oxide (SiO x ), a silicon nitride (SiN x ), a mixture thereof, and a metal comprising Ti, Cr, Ni, Cu, W, Au, Ag, or an alloy thereof.
10. The method of claim 9 , wherein the bonding layer is formed using at least one of plasma enhanced chemical vapor deposition, sputtering, and plating.
11. The method of claim 6 , further comprising dicing the first substrate.
12. The method of claim 6 , wherein the thermal expansion coefficient of the bonding layer is smaller than or equal to the thermal expansion coefficient of at least one of the first substrate and the second substrate.
13. The method of claim 6 , wherein the at least one semiconductor lamination structure comprises a first type semiconductor layer, an active layer, and a second type semiconductor layer.
14. The method of claim 13 , wherein the thermal expansion coefficient of the bonding layer is smaller than or equal to the thermal expansion coefficient of at least one of the first substrate and the second substrate, and
wherein the thermal expansion coefficient of the bonding layer is greater than or equal to the thermal expansion coefficient of at least one of the first type semiconductor layer and the second type semiconductor layer.
15. The method of claim 6 , wherein the at least one semiconductor lamination structure comprises a plurality of semiconductor lamination structures, each semiconductor lamination structure comprising a first type semiconductor layer, an active layer, and a second type semiconductor layer.
16. The method of claim 15 , further comprising dicing the first substrate after removing the bonding layer and the second substrate,
wherein dicing the first substrate comprises forming one semiconductor lamination structure of the plurality of semiconductor lamination structures on the first substrate.
17. A substrate assembly, comprising:
a first substrate;
a second substrate;
a bonding layer disposed between the first substrate and the second substrate; and
a semiconductor lamination structure arranged on the first substrate, the semiconductor lamination structure comprising a first type semiconductor layer, an active layer, and a second type semiconductor layer,
wherein the first substrate is disposed between the semiconductor lamination structure and the second substrate,
wherein the thermal expansion coefficient of the bonding layer is smaller than or equal to the thermal expansion coefficient of at least one of the first substrate and the second substrate, and
wherein sides of the first and second substrates facing each other have the same surface area.
18. The substrate assembly of claim 17 , wherein the thermal expansion coefficient of the bonding layer is greater than or equal to the thermal expansion coefficient of at least one of the first type semiconductor layer and the second type semiconductor layer.