IP Library › Granted Patent US 8,982,991
Granted Patent B2
US 8,982,991 · App. 13/655,914 · Granted Mar 17, 2015

Digital pre-distortion method and apparatus thereof for changing memory degree depending on input level

Inventor: Young-Yoon Woo (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H03F1/3247H03F3/24H03F2201/3224
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Quick Facts
Patent No.
US 8,982,991
App. No.
13/655,914
Granted
Mar 17, 2015
Kind
B2
Abstract

An apparatus and a method for operating a memory compensation Digital Pre-Distortion (DPD) are provided. In the method for operating a memory compensation DPD system, an input signal is received. An input average power of the input signal is determined. When the input average power of the input signal belongs to a non-linear section of the input average power, DPD is performed on a previous signal corresponding to a memory degree set depending on at least one non-linear section of the input average power.

Claims (41)

1. A method for operating a memory compensation Digital Pre-Distortion (DPD) system, the method comprising:

receiving an input signal;

determining an input average power of the input signal; and

when the input average power of the input signal belongs to a non-linear section of the input average power, performing DPD on a previous signal corresponding to a memory degree set depending on at least one non-linear section of the input average power, and

when the input average power of the input signal belongs to a linear section of the input average power, performing DPD on a current input signal to output an output signal.

2. The method of claim 1 , further comprising adding a signal obtained by performing DPD on the previous signal and a signal obtained by performing DPD on the current input signal to output the output signal.

3. The method of claim 2 , further comprising:

up-converting the output signal; and

amplifying the up-converted signal.

4. The method of claim 3 , further comprising:

down-converting the amplified signal;

determining a DPD correction coefficient for DPD from the down-converted amplified signal; and

outputting the DPD correction coefficient for the DPD.

5. A memory compensation Digital Pre-Distortion (DPD) system, the system comprising:

a memory compensation Digital Pre-Distorter (DPD) for receiving an input signal, determining an input average power of the input signal, and when the input average power of the input signal belongs to a non-linear section of the input average power, performing DPD on a previous signal corresponding to a memory degree set depending on at least one non-linear section of the input average power,

wherein the memory compensation DPD comprises:

an Average Power Meter (APM) for determining the input average power of the input signal,

a switch controller for providing a switch signal for performing DPD on the previous signal corresponding to the memory degree set depending on the at least one non-linear section of the input average power, and

at least one DPD for performing DPD on the previous signal depending on the switch signal.

6. The system of claim 5 , further comprising an adder for adding a signal obtained by performing DPD on the previous signal and a signal obtained by performing DPD on the current input signal to output an output signal.

7. The system of claim 6 , further comprising:

an up-converter for up-converting the output signal; and

an amplifier for amplifying the up-converted signal.

8. The system of claim 7 , further comprising:

a down-converter for down-converting the amplified signal; and

a correction algorithm unit for determining a DPD correction coefficient for DPD from the down-converted amplified signal, and outputting the DPD correction coefficient for the DPD.

9. The system of claim 5 , further comprising:

a DPD for, when the input average power belongs to a linear section of the input average power, performing DPD on a current input signal to output an output signal.

10. The system of claim 9 , further comprising:

an up-converter for up-converting the output signal; and

an amplifier for amplifying the up-converted signal.

11. The system of claim 10 , further comprising:

a down-converter for down-converting the amplified signal; and

a correction algorithm unit for determining a DPD correction coefficient for DPD from the down-converted amplified signal, and outputting the DPD correction coefficient for the DPD.

12. A method for operating a memory compensation Digital Pre-Distortion (DPD) system, the method comprising:

receiving an input signal;

measuring an input average power of the input signal;

determining a section to which the input average power of the input signal belongs;

performing DPD on a current input signal and performing DPD on a previous input signal when determined that the section to which the input average power of the input signal belongs to a non-linear section; and

adding the DPD current input signal and the DPD previous input signal and outputting an output signal; and

performing DPD on only the current input signal when determined that the section to which the input average power of the input signal belongs to a linear section.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2012
From: WOO, YOUNG-YOON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 029159/0441 →
Priority Claims (1)
KR 10-2011-0107542 · Oct 20, 2011 · national
Continuity (1)
Related Publication 20130100991A1 · Apr 25, 2013