Method for reducing the overhead associated with a virtual machine exit when handling instructions related to descriptor tables
A computerized method for efficient handling of a privileged instruction executed by a virtual machine (VM). The method comprises identifying when the privileged instruction causes a VM executed on a computing hardware to perform a VM exit; replacing a first virtual-to-physical address mapping to a second virtual-to-physical address mapping respective of a virtual pointer associated with the privileged instruction; and invalidating at least a cache entry in a cache memory allocated to the VM, thereby causing a new translation for the virtual pointer to the second virtual-to-physical address, wherein the second virtual-to-physical address provides a pointer to a physical address in a physical memory in the computing hardware allocated to the VM.
1. A computerized method for efficient handling of a privileged instruction executed by a virtual machine (VM) to prevent a VM exit, comprising:
capturing a privileged instruction, wherein the captured privileged instruction when executed causes a VM executing on a computing hardware to perform a VM exit;
without performing a VM exit, replacing a first virtual-to-physical address mapping with a second virtual-to-physical address mapping for a virtual pointer associated with the privileged instruction, wherein the first virtual-to-physical address mapping provides a mapping of a first virtual address to a first physical address and the second virtual-to-physical address mapping provides a mapping of the first virtual address to a second new physical address, the first physical address having been pointed to by only the first virtual address at the time of the replacing; and
invalidating at least a cache entry in a cache memory allocated to the VM, thereby causing a new translation for the virtual pointer using the second virtual-to-physical address mapping, wherein the second virtual-to-physical address provides a pointer to the second new physical address in a physical memory in the computing hardware allocated to the VM.
2. The computerized method of claim 1 , wherein the privileged instruction affects at least a descriptor table register.
3. The computerized method of claim 2 , wherein the privileged instruction is any one of: a load global descriptor table (LGDT) register and a load interrupt descriptor table (LIDT).
4. The computerized method of claim 3 , further comprising:
determining if a length of at least one of the global descriptor table and the interrupt descriptor table has been increased; and
filling each table having an increased length with values which when accessed cause exceptions.
5. The computerized method of claim 2 , wherein the virtual address points to a descriptor table, and further wherein the replacing of the first virtual-to-physical address mapping with the second virtual-to-physical address mapping causes access to memory by the VM to be made using a different table than prior to the replacement.
6. The computerized method of claim 1 , further comprising:
resolving conflicts between a plurality of processors sharing the physical memory, wherein the plurality of processors execute the VM.
7. The computerized method of claim 6 , wherein resolving the conflicts between the plurality of processors further comprising:
assigning for each of the plurality of processors a virtual pointer uniquely identified by each of the plurality of processors, wherein the replacement of the first virtual-to-physical address mapping results in the second virtual-to-physical address mapping that is uniquely assigned to each of the plurality of processors.
8. The computerized method of claim 1 , wherein invalidating of the cache entry is performed by an invalidation scheme defined for a memory cache in the computing hardware allocated to the VM.
9. A non-transitory computer readable medium having computer program logic recorded thereon for executing on at least one processor for handling of at least a privileged instruction executed by a virtual machine (VM), comprising:
computer program code for capturing a privileged instruction, wherein the captured privileged instruction when executed causes a VM executing on the at least one processor to perform a VM exit;
computer program code for replacing a first virtual-to-physical address mapping with a second virtual-to-physical address mapping for a virtual pointer associated with the privileged instruction instead of performing the VM exit, wherein the first virtual-to-physical address mapping provides a mapping of a first virtual address to a first physical address and the second virtual-to-physical address mapping provides a mapping of the first virtual address to a second new physical address, the first physical address having been pointed to by only the first virtual address at the time of the replacing; and
computer program code for invalidating at least a cache entry in a cache memory allocated to the VM, thereby causing a new translation for the virtual pointer using the second virtual-to-physical address mapping, wherein the second new virtual-to-physical address provides a pointer to a physical address in a physical memory in the computing hardware allocated to the VM.
10. The non-transitory computer readable medium of claim 9 , wherein the privileged instruction affects at least a descriptor table register.
11. The non-transitory computer readable medium of claim 10 , wherein the privileged instruction is any one of: a load global descriptor table (LGDT) register and a load interrupt descriptor table (LIDT).
12. The non-transitory computer readable medium of claim 11 , further comprising:
computer program code for determining if a length of at least one of the global descriptor table and the interrupt descriptor table has been increased; and
computer program code for filling each table having an increased length with values which when accessed cause exceptions.
13. The non-transitory computer readable medium of claim 9 , further comprising:
computer program code for resolving conflicts between a plurality of processors sharing the physical memory, wherein the plurality of processors execute the VM.
14. The non-transitory computer readable medium of claim 13 , wherein resolving the conflicts between the plurality of processors further comprising:
assigning for each of the plurality of processors a virtual pointer uniquely identified for each of the plurality of processors, wherein the replacement of the first virtual-to-physical address mapping results in the second virtual-to-physical address mapping that is uniquely assigned to each of the plurality of processors.
15. The non-transitory computer readable medium of claim 9 , wherein invalidating of the cache entry is performed by an invalidation scheme defined for a memory cache in the computing hardware allocated to the VM.
16. The non-transitory computer readable medium of claim 9 , wherein the virtual address points to a descriptor table, and further wherein the replacing of the first virtual-to-physical address mapping with the second virtual-to-physical address mapping causes access to memory by the VM to be made using a different table than prior to the replacement.