Memory constructions
View Patent ↗Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.
1. A memory construction comprising:
a bottom electrode;
a stack over the bottom electrode; said stack comprising chalcogenide bands alternating with non-chalcogenide bands; wherein there at least two of the chalcogenide bands and at least one of the non-chalcogenide bands;
a top electrode over the stack;
the stack including a first electrically conductive material between the to electrode and an uppermost of the chalcogenide bands;
the stack including a second electrically conductive material between a lowermost of the chalcogenide bands and the bottom electrode; and
wherein at least one of the first and second electrically conductive materials comprises carbon.
2. A memory construction comprising:
a bottom electrode;
a stack over the bottom electrode; said stack comprising chalcogenide bands alternating with non-chalcogenide bands; wherein there at least two of the chalcogenide bands and at least one of the non-chalcogenide bands;
a top electrode over the stack;
the stack including a first electrically conductive material between the to electrode and an uppermost of the chalcogenide bands;
the stack including a second electrically conductive material between a lowermost of the chalcogenide bands and the bottom electrode; and
wherein both of the first and second electrically conductive materials comprise carbon.
3. The memory construction of claim 2 wherein the at least one non-chalcogenide band comprises carbon.
4. The memory construction of claim 3 wherein the chalcogenide and non-chalcogenide bands have thicknesses of less than or equal to about 5 nanometers.
5. The memory construction of claim 3 wherein:
the stack has a width along a cross-section;
there is a first interface between the top electrode and the first electrically conductive material;
there is a second interface between the bottom electrode and the second electrically conductive material;
the top electrode has a dimension along the first interface at least as long as the width of the stack; and
the bottom electrode is configured as a beam having a dimension along the second interface at least as long as the width of the stack.
6. The memory construction of claim 3 wherein:
the stack has a width along a cross-section;
there is a first interface between the top electrode and the first electrically conductive material;
there is a second interface between the bottom electrode and the second electrically conductive material;
the top electrode has a dimension along the first interface at least as long as the width of the stack; and
the bottom electrode has a dimension along the second interface that is less than the width of the stack.
7. The memory construction of claim 6 wherein the bottom electrode is a lance configuration.
8. The memory construction of claim 6 wherein the bottom electrode is an angled plate configuration.
9. The memory construction of claim 6 wherein the bottom electrode is a container configuration.
10. A memory construction comprising:
a bottom electrode;
a stack over the bottom electrode; said stack comprising chalcogenide bands alternating with non-chalcogenide bands; wherein there at least two of the chalcogenide bands and at least one of the non-chalcogenide bands;
a top electrode over the stack;
the stack including a first electrically conductive material between the to electrode and an uppermost of the chalcogenide bands;
the stack including a second electrically conductive material between a lowermost of the chalcogenide bands and the bottom electrode; and
a select device electrically coupled to the bottom electrode.
11. The memory construction of claim 10 wherein the select device is a diode, a field effect transistor or a bipolar junction transistor.