Apparatus and method for forming semiconductor contacts

1. A method comprising:

forming a germanium fin structure over a silicon substrate, wherein the germanium fin structure comprises:

a channel connected between a first drain/source region and a second drain/source region;

depositing an N+ amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure; and

performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.

2. The method of claim 1 , wherein:

the first temperature is in a range from about 550 degrees to about 600 degrees.

3. The method of claim 1 , wherein:

the second temperature is in a range from about 620 degrees to about 650 degrees.

4. The method of claim 1 , further comprising:

depositing an inter-layer dielectric (ILD) layer over the substrate, wherein the germanium fin structure is embedded in the ILD layer;

forming a first opening over the first drain/source region in the ILD layer;

forming a second opening over the second drain/source region in the ILD layer;

filling the first opening and the second opening with N+ amorphous silicon;

performing a solid phase epitaxial regrowth process on N+ amorphous silicon to form a N+ silicon region; and

performing a CMP process on the ILD layer until the N+ silicon region is exposed.

5. The method of claim 4 , wherein:

the N+ silicon region wraps the first drain/source region around three sides.

6. The method of claim 4 , wherein:

the N+ silicon region is formed over the first drain/source region.

7. A method comprising:

forming a germanium fin over a silicon substrate, wherein the germanium fin comprises:

a first drain/source region;

a second drain/source region; and

a channel coupled between the first drain/source region and the second drain/source region;

forming a gate structure over the channel, wherein the gate structure comprises:

a gate dielectric layer; and

a gate electrode layer formed over the gate dielectric layer;

depositing a first amorphous silicon layer over the first drain/source region at a first temperature;

depositing a second amorphous silicon layer over the second drain/source region at a second temperature; and

performing a solid phase epitaxial regrowth process on the first amorphous silicon layer and the second amorphous silicon layer at a third temperature.

8. The method of claim 7 , wherein:

the first temperature is in a range from about 550 degrees to about 600 degrees;

the second temperature is in a range from about 550 degrees to about 600 degrees; and

the third temperature is in a range from about 620 degrees to about 650 degrees.

9. The method of claim 7 , further comprising:

depositing an inter-layer dielectric (ILD) layer over the substrate, wherein the first drain/source region and the second drain/source region are embedded in the ILD layer;

forming a first opening over the first drain/source region, wherein the first opening is of a dimension approximately equal to a dimension of the first drain/source region;

forming a second opening over the second drain/source region, wherein the second opening is of a dimension approximately equal to a dimension of the second drain/source region;

depositing amorphous silicon in the first opening and the second opening; and

performing a solid phase epitaxial regrowth process on the amorphous silicon.

10. The method of claim 7 , further comprising:

depositing an inter-layer dielectric (ILD) layer over the substrate, wherein the first drain/source region and the second drain/source region are embedded in the ILD layer;

forming a first opening over the first drain/source region, wherein the first opening is of a dimension greater than a dimension of the first drain/source region;

forming a second opening over the second drain/source region, wherein the second opening is of a dimension greater than a dimension of the second drain/source region;

depositing amorphous silicon in the first opening and the second opening; and

performing a solid phase epitaxial regrowth process on the amorphous silicon.

11. The method of claim 10 , further comprising:

after the step of performing a solid phase epitaxial regrowth process on the amorphous silicon, applying a CMP process to the ILD layer; and

forming a first N+ silicon structure over the first drain/source region, wherein the first N+ silicon structure wraps the first drain/source region around three sides; and

forming a second N+ silicon structure over the second drain/source region, wherein the second N+ silicon structure wraps the second drain/source region around three sides.

12. The method of claim 11 , further comprising:

forming a first metal contact over the first N+ silicon structure; and

forming a second metal contact over the second N+ silicon structure.