IP Library Granted Patent US 9,165,133
Granted Patent B2
US 9,165,133 · App. 13/661,596 · Granted Oct 20, 2015

Systems and methods of device authentication including features of circuit testing and verification in connection with known board information

Inventors: George Bernard La Fever (Huntsville, AL); Iser B. Flaum (Fullerton, CA)
Assignee: Electronic Warfare Associates, Inc.
G06F21/44G06F21/73G06F21/76G06F2221/2103G06F2221/2145
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Quick Facts
Patent No.
US 9,165,133
App. No.
13/661,596
Granted
Oct 20, 2015
Kind
B2
Abstract

A method and system for authenticating a device, board, assembly or system includes obtaining or processing test/scan information provided via extraction of ECID or other unique identifying information regarding a board. A re-authentication process is performed to verify that the board contains only legitimate ECID or other uniquely identified devices, via comparison of re-extracted codes of devices at known positions against a reference record, the reference record being established by an initial authentication process that utilizes information regarding authentic/unique ECID or other uniquely identified codes of devices delivered to populate the board to derive the reference record for the device.

Claims (19)

1. A device comprising:

application circuitry;

one or more scan or boundary scan components adapted to shift in and shift out test scans of the application circuitry;

a unique code adapted to uniquely identify the device;

an interrogation code component adapted to interact with interrogation information having an interrogation code applied to the device;

a hidden seed element which is of unique value per device of a given type, used in a signature generation process for the device, wherein the hidden seed is involved with though not directly accessible during authentication of the device, not extractable from the device, and initially known only to an IC fabricator that fabricated the device;

a signature encryption component that provides an output signature code that is unique to the device, for given interrogation information, the output signature code being a function of the hidden seed;

wherein the device and/or signature encryption engine are configured to process a test/scan procedure performed on the device, the test/scan procedure comprising:

shifting in and shifting out, via one or more scan or boundary scan components, test scans of the application circuitry, each test scan comprising the interrogation information;

performing a signature generation process within the device, via the signature encryption component, using the hidden seed element which is of unique value per device of a given type, the signature being a function of algorithmic interaction with at least the hidden seed and the interrogation code, and consisting of a signature code based only on the algorithmic interaction such that the hidden seed is not discernable from the signature code, wherein the hidden seed element is not extractable from the device, and is initially known only to the IC fabricator that fabricated the device; and

providing the signature code that is unique to the device, for given interrogation information as output, wherein authenticity of the signature code can only be determined by knowledge of the device's hidden seed and the interrogation code;

wherein, as a function of (i) the hidden seed being inaccessible from the device and unlearnable during authentication via the interrogation codes of the test/scan procedure and (ii) ability to perform the test scans without knowing the hidden seed, the device is counterfeit-resistant.

2. The device of claim 1 wherein arbitrary interrogation codes may be used in the signature generation process as a function of the hidden seed.

3. A method of providing defense against supply chain interception of a device, the method comprising:

the device and/or a signature encryption engine of the device processing a test/scan procedure performed on the device, the device having a signature encryption component as well as a hidden seed element that is involved with though not directly accessible during authentication of the device, the test/scan procedure including:

shifting in and shifting out, via one or more scan or boundary scan components, test scans of application circuitry, each test scan comprising interrogation information having an interrogation code;

performing a signature generation process within the device, via the signature encryption component, using the hidden seed element which is of unique value per device of a given type, the signature being a function of algorithmic interaction with at least the hidden seed and the interrogation code, and consisting of a signature code based only on the algorithmic interaction such that the hidden seed is not discernable from the signature code, wherein the hidden seed element is not extractable from the device, and is initially known only to the IC fabricator that fabricated the device; and

providing the signature code that is unique to the device, for given interrogation information as output, wherein authenticity of the signature code can only be determined by knowledge of the device's hidden seed and the interrogation code;

wherein, as a function of (i) the hidden seed being inaccessible from the device and un-learnable during authentication via the interrogation codes of the test/scan procedure and (ii) ability to perform the test scans without knowing the hidden seed, the device is counterfeit-resistant.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2023
From: ELECTRONIC WARFARE ASSOCIATES, INC.
To: CORELIS, INC.
Reel/Frame 063772/0251 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2013
From: LA FEVER, GEORGE BERNARD; FLAUM, ISER B.
To: ELECTRONIC WARFARE ASSOCIATES, INC.
Reel/Frame 029706/0657 →
Continuity (2)
Provisional Application 61552074 · Oct 27, 2011
Related Publication 20130125204A1 · May 16, 2013