IP Library › Granted Patent US 9,037,943
Granted Patent B2
US 9,037,943 · App. 13/662,160 · Granted May 19, 2015

Identification of non-volatile memory die for use in remedial action

Inventors: Ravi H. Motwani (San Diego, CA); Kiran Pangal (Fremont, CA)
Assignee: Intel Corporation
H03M13/2927H03M13/09H03M13/1102H03M13/293H03M13/2948H03M13/2957
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,037,943
App. No.
13/662,160
Granted
May 19, 2015
Kind
B2
Abstract

Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die.

Claims (32)

1. An apparatus comprising:

a first block configured to encode data to be stored in a non-volatile memory as a codeword, to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory, and to generate respective error detection codes for the plurality of die; and

a second block coupled to the first block and configured to identify a first die of the plurality of die for use in remedial action, based on a determination related to the error detection codes that more sub-portions of a first portion of the codeword stored on the first die include an error than sub-portions of a second portion of the codeword stored on a second die of the plurality of die.

2. The apparatus of claim 1 , wherein the second block is configured to perform the identification in response to a failed attempt by the first block to decode the codeword.

3. The apparatus of claim 1 , further comprising a memory controller, wherein the memory controller comprises the first and second blocks.

4. The apparatus of claim 1 , wherein the remedial action comprises an attempt to reconstruct a portion of the codeword read from the first die.

5. The apparatus of claim 1 , wherein the remedial action comprises another attempt to decode the codeword in a manner different than the failed attempt.

6. The apparatus of claim 5 , wherein the another attempt to decode the codeword includes a designation of bits of the first die as erasures.

7. The apparatus of claim 5 , wherein the another attempt to decode the codeword includes a re-read of the codeword from a different demarcation than was used in the failed attempt.

8. The apparatus of claim 1 , wherein the determination comprises use of an error detection code generated from the first portion of the codeword.

9. The apparatus of claim 8 , wherein the error detection code is used to count sub-portions of the first portion of the codeword that include an error.

10. The apparatus of claim 9 , wherein the error detection code comprises a plurality of parity bits.

11. The apparatus of claim 10 , wherein the plurality of parity bits are calculated based on respective sub-portions of the first portion of the codeword.

12. The apparatus of claim 9 , wherein the plurality of parity bits are XOR results of bits of the respective sub-portions of the first portion.

13. The apparatus of claim 1 , wherein the respective error detection codes are stored on respective die.

14. A system comprising:

a storage drive comprising a plurality of die of non-volatile memory; and

a controller having a first block to encode data to be stored in the non-volatile memory as a codeword, to store respective portions of the codeword in a distributed manner across the plurality of die of the non-volatile memory, and to generate respective error detection codes for the plurality of die, and a second block coupled to the first block to identify a first die of the plurality of die for use in remedial action, based on a determination related to the error detection codes, that more sub-portions of a first portion of the codeword stored on the first die include an error than sub-portions of a second portion of the codeword stored on a second die of the plurality of die.

15. The system of claim 14 , further comprising a touch screen display.

16. At least one non-transitory computer-readable memory comprising instructions that, responsive to execution of the instructions by a computing device, enable the computing device to operate:

a first block configured to encode data to be stored in a non-volatile memory as a codeword, to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory, and to generate respective error detection codes for the plurality of die; and

a second block configured to identify, responsive to a failed attempt by the first block to decode the codeword, a first die of the plurality of die for use in remedial action based on a determination related to the error detection codes that more sub-portions of a first portion of the codeword stored on the first die include an error than sub-portions of a second portion of the codeword stored on a second die of the plurality of die.

17. The at least one non-transitory computer-readable medium of claim 16 , wherein the remedial action comprises an attempt to reconstruct a portion of the codeword read from the first die.

18. The at least one non-transitory computer-readable medium of claim 16 , wherein the remedial action comprises another attempt to decode the codeword in a manner different than the failed attempt, including a designation of bits of the first die as erasures.

19. The at least one non-transitory computer-readable medium of claim 16 , wherein the remedial action comprises another attempt to decode the codeword from a different demarcation than was used in the failed attempt.

20. The at least one non-transitory computer-readable medium of claim 16 , wherein the error detection code is used to count sub-portions of the first portion of the codeword that include an error.

21. The at least one non-transitory computer-readable medium of claim 20 , wherein the error detection code comprises a plurality of parity bits calculated based on respective sub-portions of the first portion of the codeword, and wherein the plurality of parity bits are XOR results of bits of the respective sub-portions of the first portion.

22. A computer-implemented method, comprising:

reading, by a controller from a plurality of die of non-volatile memory, respective portions of a codeword stored in a distributed manner across the plurality of die;

identifying, by the controller in response to a failed attempt to decode the codeword, a first die of the plurality of die, based on a determination related to respective error detection codes associated with the plurality of die, that more sub-portions of a first portion of the codeword stored on the first die include an error than sub-portions of a second portion of the codeword stored on a second die of the plurality of die; and

performing, by the controller, remedial action using the first die.

23. The computer-implemented method of claim 22 , wherein performing the remedial action comprises attempting to reconstruct a portion of the codeword read from the first die, attempting to decode the codeword in a manner different than the failed attempt, or re-reading of the codeword from a different demarcation than was used in the failed attempt.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2012
From: MOTWANI, RAVI H.; PANGAL, KIRAN
To: INTEL CORPORATION
Reel/Frame 029202/0239 →
Continuity (1)
Related Publication 20140122963A1 · May 1, 2014