Electrostatic discharge protection device

1. An electrostatic discharge protection device, comprising: a P-type substrate set as floating; a first common N-well formed in the P-type substrate; a first common N-doped region formed in the first common N-well; a first common P-doped region formed in the first common N-well; a second common N-well formed in the P-type substrate; a second common N-doped region formed in the second common N-well, wherein the second common N-doped region is electrically connected to a reference voltage node; a second common P-doped region formed in the second common N-well; a third common P-doped region formed between the first common N-well and the second common N-well on the P-type substrate, wherein the third common P-doped region is electrically connected to the first common N-doped region and the second common P-doped region; and a plurality of peripheral N-wells formed in the P-type substrate, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and the N-type doped region is electrically connected to the first common P- doped region and a bus.

2. The electrostatic discharge protection device as claimed in claim 1 , wherein the first common P-doped region and the first common N-well form a first common diode, the second common P-doped region and the second common N-well form a second common diode, wherein when an electrostatic discharge event occurs between any of the I/O terminals and the reference voltage node, the first and the second common diodes are forward-biased.

3. The electrostatic discharge protection device as claimed in claim 1 , wherein the second common N-well, the P-type substrate, and the first common N-well form a first parasitic BJT, and the first common P-doped region, the first common N-well, and the P-type substrate form a second parasitic BJT, when an electrostatic discharge event occurs at any of the I/O terminals, the first BJT and the second parasitic BJT are triggered to ON.

4. An electrostatic discharge protection device, comprising:

a P-type semiconductor substrate set as floating;

a first N-well and a second N-well formed in the P-type substrate;

a first P-doped region and a second P-doped region formed in the first N-well and the second N-well respectively, wherein the first N-well and the first P-doped region form a first diode, the second N-well and the second P-doped region form a second diode;

a first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively; and

a third P-doped region formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region, wherein the first P-doped region is electrically connected to an I/O terminal, the second N-doped region is electrically connected to a reference voltage node, the second N-well, the P-type substrate and the first N-well form a first parasitic BJT, and the first P-doped region, the first N-well and the P-type substrate form a second parasitic BJT, when an electrostatic discharge event occurs at the I/O terminal, the first and the second parasitic BJTs are triggered to ON.

5. The electrostatic discharge protection device as claimed in claim 4 further comprises:

a third N-well formed in the P-type substrate;

a third N-doped region formed in the third N-well and electrically connected to the I/O terminal;

a fourth P-doped region formed in the third N-well, the fourth P-doped region being electrically connected to the second N-doped region and the reference voltage node, wherein the fourth P-doped region and the third N-well form a third diode.

6. The electrostatic discharge protection device as claimed in claim 4 , wherein a distance between the first N-well and the second N-well is less than 5 um.

7. An electrostatic discharge protection device, comprising:

a P-type semiconductor substrate set as floating;

a first N-well and a second N-well formed in the P-type substrate;

a first P-doped region and a second P-doped region formed in the first and the second N-well respectively, wherein the first N-well and the first P-doped region form a first diode, the second N-well and the second P-doped region form a second diode, and the first P-doped region is electrically connected to an I/O terminal;

a first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively, wherein the second N-doped region is electrically connected to a reference voltage node; and

a gate structure formed on the P-type substrate, wherein the gate structure is disposed between the first N-well and the second N-well, and the gate structure is electrically connected to the first N-doped region and the second P-doped region.

8. The electrostatic discharge protection device as claimed in claim 7 , wherein the gate structure, the first N-well, and the second N-well and the P-type substrate form a parasitic MOSFET, wherein when an electrostatic discharge event occurs at the I/O terminal, the parasitic MOSFET is triggered to ON.

9. The electrostatic discharge protection device as claimed in claim 7 further comprises:

a third N-well formed in the P-type substrate;

a third N-doped region formed in the third N-well; and

a third P-doped region formed in the third N-well, wherein the third P-doped region and the third N-well form a third diode.

10. The electrostatic discharge protection device as claimed in claim 9 , wherein the third P-doped region and the third N-doped region are electrically connected to the reference voltage node and the I/O terminal respectively.

11. The electrostatic discharge protection device as claimed in claim 7 , wherein a distance between the first N-well and the second N-well is less than 1 um.

12. An electrostatic discharge protection device, comprising:

a P-type semiconductor substrate set as floating;

a first N-well and a second N-well formed in the P-type substrate;

a first P-doped region and a second P-doped region formed in the first N-well and the second N-well respectively, wherein the first N-well and the first P-doped region form a first diode, the second N-well and the second P-doped region form a second diode;

a first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively; and

a third P-doped region formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region;

a third N-well formed in the P-type substrate;

a third N-doped region formed in the third N-well and electrically connected to an I/O terminal;

a fourth P-doped region formed in the third N-well, wherein the fourth P-doped region and the third N-well form a third diode.

13. The electrostatic discharge protection device as claimed in claim 12 further comprises:

a fourth N-well formed in the P-type substrate;

a fourth N-doped region formed in the fourth N-well and electrically connected to the first P-doped region; and

a fifth P-doped region formed in the fourth N-well and electrically connected to the I/O terminal, wherein the fifth P-doped region and the fourth N-well form a fourth diode;

wherein the fourth P-doped region being electrically connected to the second N-doped region and the reference voltage node.

14. The electrostatic discharge protection device as claimed in claim 12 further comprises:

a fifth N-well formed in the P-type substrate;

a fifth N-doped region formed in the fifth N-well, the fifth N-doped region being electrically connected to a reference voltage node and the fourth P-doped region; and

a sixth P-doped region formed in the fifth N-well and electrically connected to the second N-doped region, wherein the sixth P-doped region and the fifth N-well form a fifth diode;

wherein the first P-doped region is electrically connected to the I/O terminal.

15. The electrostatic discharge protection device as claimed in claim 12 , wherein a distance between the first N-well and the second N-well is less than 5 um.