Memory array with a pair of memory-cell strings to a single conductive pillar
An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory cell has a respective portion of a first charge trap adjacent to the conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap. Each second memory cell has a respective portion of a second charge trap adjacent to the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap. Each first control gate is electrically isolated from each second control gate. A single select transistor may selectively couple the plurality of first memory cells and the plurality of second memory cells to one of a source line and a data line.
1. A memory array, comprising:
a substantially vertical conductive pillar;
a plurality of first memory cells on a first side of the substantially vertical conductive pillar coupled in series by the substantially vertical conductive pillar, each first memory cell comprising a respective portion of a first charge trap adjacent to the first side of the substantially vertical conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap;
a plurality of second memory cells on a second side of the substantially vertical conductive pillar, opposite to the first side of the substantially vertical conductive pillar, coupled in series by the substantially vertical conductive pillar, each second memory cell comprising a respective portion of a second charge trap adjacent to the second side of the substantially vertical conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap; and
a single select transistor that selectively electrically couples both the plurality of first memory cells and the plurality of second memory cells to a data line;
wherein each first control gate is electrically isolated from each second control gate; and
wherein respective ones of the first memory cells of the plurality of first memory cells are respectively at same vertical levels as respective ones of the second memory cells of the plurality of second memory cells.
2. The memory array of claim 1 , wherein the first charge trap is electrically isolated from the second charge trap.
3. The memory array of claim 1 , wherein the substantially vertical conductive pillar is a first substantially vertical conductive pillar, and wherein the single select transistor is adjacent to a second substantially vertical conductive pillar coupled to the first substantially vertical conductive pillar.
4. The memory array of claim 1 , wherein the substantially vertical conductive pillar forms a channel for both the plurality of first memory cells and the plurality of second memory cells.
5. The memory array of claim 1 , further comprising another single select transistor that selectively electrically couples the plurality of first memory cells and the plurality of second memory cells to a source line.
6. A memory array, comprising:
a first conductive pillar coupling a plurality of first memory cells in series and a plurality of second memory cells in series, each first memory cell comprising a respective portion of a first charge trap adjacent to a first side of the first conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap, each second memory cell comprising a respective portion of a second charge trap adjacent to a second side of the first conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap, wherein each first control gate is electrically isolated from each second control gate; and
a second conductive pillar coupling a plurality of third memory cells in series and a plurality of fourth memory cells in series, each third memory cell comprising a respective portion of a third charge trap adjacent to a first side of the second conductive pillar and a respective third control gate adjacent to the respective portion of the third charge trap, each fourth memory cell comprising a respective portion of a fourth charge trap adjacent to a second side of the second conductive pillar and a respective fourth control gate adjacent to the respective portion of the fourth charge trap, wherein each third control gate is electrically isolated from each fourth control gate;
wherein each first control gate and a respective one of the third control gates are electrically coupled and are portions of a respective access line that is between the first conductive pillar and the second conductive pillar and that extends from the first charge trap to the third charge trap; and
wherein at least one first memory cell, at least one second memory cell, at least one third memory cell, and at least one fourth memory cell are at a same vertical level.
7. The memory array of claim 6 , wherein the first charge trap is electrically isolated from the second charge trap and the third charge trap is electrically isolated from the fourth charge trap.
8. The memory array of claim 6 , wherein the first conductive pillar forms a channel for both the plurality of first memory cells and the plurality of second memory cells and the second conductive pillar forms a channel for both the plurality of third memory cells and the plurality of fourth memory cells.
9. The memory array of claim 6 , further comprising a single first select transistor that selectively electrically couples both the plurality of first memory cells and the plurality of second memory cells to a data line and a single second select transistor that selectively electrically couples both the plurality of third memory cells and the plurality of fourth memory cells to the data line.
10. The memory array of claim 9 , further comprising a single third select transistor that selectively electrically couples both the plurality of first memory cells and the plurality of second memory cells to a source line and a single fourth select transistor that selectively electrically couples both the plurality of third memory cells and the plurality of fourth memory cells to the source line.
11. The memory array of claim 10 , wherein a select gate of the single first select transistor is electrically isolated from a select gate of the single second select transistor.
12. The memory array of claim 10 , wherein a select gate of the single third select transistor is electrically coupled to a select gate of the single fourth select transistor.
13. A memory array, comprising:
a substantially vertical conductive pillar;
a first charge trap that curves around a first curved side of the substantially vertical conductive pillar and that terminates at an isolation region;
a second charge trap that curves around a second curved side of the substantially vertical conductive pillar and that terminates at the isolation region so that the isolation region electrically isolates the first charge trap from the second charge trap;
a first conductor at a first vertical elevation that curves around a first portion of a curved surface of the first charge trap and that terminates at the isolation region and a second conductor at a second vertical elevation that curves around a second portion of the curved surface of the first charge trap and that terminates at the isolation region, the first conductor and the first portion of the curved surface of the first charge trap defining a first memory cell of a first string of memory cells coupled in series by the substantially vertical conductive pillar and the second conductor and the second portion of the curved surface of the first charge trap defining a second memory cell of the first string of memory cells; and
a third conductor at the first vertical elevation that curves around a first portion of a curved surface of the second charge trap and that terminates at the isolation region so that the isolation region electrically isolates the first conductor from the third conductor and a fourth conductor at the second vertical elevation that curves around a second portion of the curved surface of the second charge trap and that terminates at the isolation region so that the isolation region electrically isolates the second conductor from the fourth conductor, the third conductor and the first portion of the curved surface of the second charge trap defining a first memory cell of a second string of memory cells coupled in series by the substantially vertical conductive pillar and the fourth conductor and the second portion of the curved surface of the second charge trap defining a second memory cell of the second string of memory cells.
14. The memory array of claim 13 , further comprising a single select transistor that selectively electrically couples both the first and second strings of memory cells to a data line.
15. The memory array of claim 14 , wherein the single select transistor is a first single select transistor, and further comprising a second single select transistor that selectively electrically couples both the first and second strings of memory cells to a source line.
16. The memory array of claim 15 , wherein the substantially vertical conductive pillar is a first substantially vertical conductive pillar, wherein the first single select transistor is adjacent to a second substantially vertical conductive pillar that is between and coupled to the first substantially vertical conductive pillar and the data line, and wherein the second single select transistor is adjacent to a third substantially vertical conductive pillar that is between and coupled to the first substantially vertical conductive pillar and the source line.
17. A memory array, comprising:
a first string of serially coupled memory cells adjacent to a first side of a substantially vertical conductive pillar;
a second string of serially coupled memory cells adjacent to a second side of the substantially vertical conductive pillar;
a first single select transistor that selectively electrically couples both the first string of serially coupled memory cells and the second string of serially coupled memory cells to a source line;
a second single select transistor that selectively electrically couples both the first string of serially coupled memory cells and the second string of serially coupled memory cells to a data line;
wherein the first string of serially coupled memory cells is electrically isolated from the second string of serially coupled memory cells;
wherein the substantially vertical conductive pillar forms a channel for both of the first and the second strings of serially coupled memory cells; and
wherein respective ones of the memory cells of the first string of serially coupled memory cells are respectively at same vertical levels as respective ones of the memory cells of the second string of serially coupled memory cells.
18. The memory array of claim 17 , wherein each of the memory cells of the first string of serially coupled memory cells comprises a first charge storage node adjacent to the first side of the substantially vertical conductive pillar and a first control gate adjacent to the charge storage node, wherein each of the memory cells of the second string of serially coupled memory cells comprises a second charge storage node adjacent to the second side of the substantially vertical conductive pillar and a second control gate adjacent to the second charge storage node.
19. The memory array of claim 18 , wherein the first charge storage node is electrically isolated from the second charge storage node and the first control gate is electrically isolated from the second control gate.
20. The memory array of claim 18 , wherein the first charge storage node is interposed between the first side of the substantially vertical conductive pillar and the first control gate and the second charge storage node is interposed between the second side of the substantially vertical conductive pillar and the second control gate.