Method for producing semiconductor device and semiconductor device
View Patent ↗A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.
1. A semiconductor device including two surround gate transistors, the device comprises:
a first fin-shaped silicon layer on a substrate;
a second fin-shaped silicon layer on the substrate, the first fin-shaped silicon layer and the second fin-shaped silicon layer connected to each other at ends thereof and define a closed loop;
a first insulating film around the first fin-shaped silicon layer and the second fin-shaped silicon layer;
a first pillar-shaped silicon layer on the first fin-shaped silicon layer and having a width equal to a width of the first fin-shaped silicon layer;
a second pillar-shaped silicon layer on the second fin-shaped silicon layer and having a width equal to a width of the second fin-shaped silicon layer;
a first diffusion layer in an upper portion of the first fin-shaped silicon layer and a lower portion of the first pillar-shaped silicon layer;
a second diffusion layer in an upper portion of the first pillar-shaped silicon layer;
a third diffusion layer in an upper portion of the second fin-shaped silicon layer and a lower portion of the second pillar-shaped silicon layer;
a fourth diffusion layer in an upper portion of the second pillar-shaped silicon layer;
a silicide in upper portions of the first and third diffusion layers in the upper portion of the first and second fin-shaped silicon layers;
a first gate insulating film around the first pillar-shaped silicon layer;
a first metal gate electrode around the gate insulating film;
a second gate insulating film around the second pillar-shaped silicon layer;
a second metal gate electrode around the second gate insulating film;
a metal gate line connected to the first metal gate electrode and to the second metal gate electrode and extending in a direction perpendicular to a direction of the first fin-shaped silicon layer and the second fin-shaped silicon layer;
a first contact on the first and second diffusion layers and directly connected to the first and second diffusion layers; and
a second contact on the third diffusion layer and directly connected to the third diffusion layer.
2. The semiconductor device of claim 1 , further comprising a third contact on the metal gate line and spaced apart from first contact.
3. The semiconductor device of claim 1 , wherein the first and second pillar-shaped silicon layers reside adjacent to one another on the first and second fin-shaped silicon layers and equidistant from the ends thereof.