Jog design in integrated circuits
A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.
1. A device comprising:
an active region in a semiconductor substrate, wherein the active region comprises a first edge and a second edge;
a gate strip over and crossing the active region, wherein the gate strip comprises a third edge and a fourth edge parallel to each other, with both the third edge and the fourth edge extending from the first edge to the second edge;
a jog overlapping the active region and connected to the gate strip to form a continuous region, wherein the jog is on a first side of the gate strip, wherein the jog comprises a fifth edge and a sixth edge parallel to the first edge, with the fifth edge overlapping the active region;
a first contact plug at a same level as the gate strip, wherein the first contact plug is on the first side of the gate strip; and
a second contact plug over the jog and the first contact plug, wherein the second contact plug electrically interconnects the first contact plug and the jog.
2. The device of claim 1 further comprising:
a first Inter-Layer Dielectric (ILD), wherein the gate strip and the jog are disposed in the first ILD;
an etch stop layer over the first ILD, the gate strip, and the first contact plug; and
a second ILD over the etch stop layer, wherein an upper portion of the second contact plug is disposed in the second ILD.
3. The device of claim 1 , wherein the second contact plug comprises a bottom surface, and wherein the bottom surface comprises:
a first portion contacting a top surface of a portion of the first contact plug;
a second portion contacting a top surface of an inter-layer dielectric; and
a third portion contacting a top surface of the jog, wherein bottom surfaces of the first portion, the second portion, and the third portion are substantially coplanar.
4. The device of claim 1 , wherein the second contact plug has an L-shape in a top view of the second contact plug and the semiconductor substrate, wherein the L-shape comprises a first leg and a second leg connected to the first leg, with the first leg contacting the first contact plug, and the second plug contacting the jog.
5. The device of claim 1 , wherein an entirety of the jog overlaps the active region, and wherein the gate strip comprises:
a first portion overlapping the active region; and
second portions overlapping isolation regions on opposite sides of the active region.
6. The device of claim 1 , wherein the jog and the gate strip in combination form:
a gate electrode comprising a first portion in the jog, and a second portion in the gate strip, wherein the first and the second portions are formed of a same material, with no interface therebetween; and
a gate dielectric comprising:
a bottom portion underlying the jog and the gate strip; and
sidewall portions on sidewalls of the gate electrode.
7. The device of claim 1 , wherein the fifth edge is between, and is misaligned from, the first edge and the second edge.
8. The device of claim 1 , wherein the sixth edge overlaps the active region, and the sixth edge is between the first and the second edge.
9. A device comprising:
an active region in a semiconductor substrate, wherein the active region comprises a first edge and a second edge opposite to each other;
a first gate strip, a second gate strip, and a third gate strip parallel to each other, and over and crossing the active region, wherein the second gate strip is between the first gate strip and the second gate strip, and the second gap strip overlaps the first edge and the second edge;
a jog over the active region and connected to the second gate strip, wherein the jog is between the first gate strip and the second gate strip, and wherein the jog and the second gate strip in combination comprise:
a continuous gate electrode; and
a continuous gate dielectric comprising a first portion overlapped by the continuous gate electrode and a second portion on a sidewall of the continuous gate electrode;
a source/drain region in the active region and between the first gate strip and the second gate strip;
a first contact plug at a same level as the first gate strip, wherein the first contact plug is over and connected to the source/drain region; and
a second contact plug over, and interconnecting, the first contact plug and the jog, wherein in a top view of the device, an entirety of the jog is closer to the first edge than an entirety of the first contact plug, and an entirety of portions of the first contact pug overlapping, the active region is closer to the second edge than an entirety of the jog.
10. The device of claim 9 , wherein the second contact plug comprises a first portion overlapping a portion of the first contact plug, and a second portion misaligned with the first contact plug.
11. The device of claim 9 further comprising:
a first Inter-Layer Dielectric (ILD), wherein the first gate strip and the jog are disposed in the first ILD;
an etch stop layer over the first ILD, the first gate strip, and the first contact plug; and
a second ILD over the etch stop layer, wherein the second contact plug is disposed in the second ILD.
12. The device of claim 9 , wherein the jog has a first width, the second gate strip has a second width, with the first width and the second width measured perpendicular to a longitudinal direction of the second gate strip, and wherein a ratio of the first width to the second width is greater than about 0.13.
13. The device of claim 9 , wherein the second contact plug has an L-shape comprising a first leg and a second leg connected to the first leg, with the first leg contacting the first contact plug, and the second contact plug contacting the jog.
14. The device of claim 9 , wherein an entirety of the jog overlaps the active region, and wherein the second gate strip comprises portions overlapping isolation regions on opposite sides of the active region.
15. A method comprising:
forming a gate strip of a MOS device, wherein the gate strip comprises a strip portion and a jog over an active region, with a first edge of the jog joining a second edge of the strip portion, wherein the strip portion and the jog in combination comprise:
a continuous gate electrode comprising a first portion in the strip portion and a second portion in the jog; and
a continuous gate dielectric comprising a first portion in the strip portion and a second portion in the jog, wherein the strip portion overlaps a third edge and a fourth edge of the active region, and the jog comprises a portion overlapping the active region, wherein the portion of the jog comprises a fifth edge and a sixth edge perpendicular to the third edge, with the fifth edge overlapping the active region and misaligned from the third edge and the fourth edge;
forming a first Inter-Layer Dielectric (ILD), with the gate strip being in the first ILD;
forming a first contact plug in the first ILD and connected to a source/drain region of the MOS device;
forming a second ILD over the first ILD;
forming an opening in the second ILD, wherein a portion of the first contact plug, a portion of the jog, and a portion of the first ILD between the jog and the first contact plug are exposed through the opening; and
filling the opening to form a second contact plug.
16. The method of claim 15 , wherein the step of forming the opening comprises:
performing a first etch step on the second ILD to form a first opening in the second ILD, wherein the portion of the first contact plug is exposed through the first opening; and
performing a second etch step on the second ILD to expose the portion of the jog, wherein the portion of the jog is exposed through the second opening, and wherein the first opening and the second opening are connected to each other to form the opening.
17. The method of claim 15 , wherein the strip portion and the jog are formed simultaneously in same process steps.
18. The method of claim 15 further comprising coupling the continuous gate electrode to a constant voltage to turn off the MOS device.
19. The method of claim 15 , wherein the gate strip overlaps a first edge and a second edge of the active region, wherein the first and the second edges are opposite edges of the active region, and wherein in a top view of the MOS device, an entirety of the jog overlaps the active region.