IP Library Granted Patent US 8,628,674
Granted Patent B2
US 8,628,674 · App. 13/682,009 · Granted Jan 14, 2014

Method for trimming a structure obtained by the assembly of two plates

Inventors: Marc Zussy (St. Egreve, FR); Bernard Aspar (Rives, FR); Chrystelle Lagahe-Blanchard (St. Joseph de Riviere, FR); Hubert Moriceau (St. Egreve, FR)
Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives; Soitec
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Quick Facts
Patent No.
US 8,628,674
App. No.
13/682,009
Granted
Jan 14, 2014
Kind
B2
Abstract

A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

Claims (16)

1. A method for assembly of two wafers comprising:

a) providing a first wafer and a second wafer each with a chamfered edge region;

b) forming a fragile zone inside the first wafer;

c) bonding the first wafer and the second wafer, wherein no bonding occurs between the two wafers in the chamfered edge region of the first wafer and in the chamfered edge region of the second wafer;

d) trimming the chamfered edge region of the first wafer where the no bonding occurs by etching, wherein the etching forms in the first wafer a pedestal resting entirely on a contact face of the second wafer and supporting a remaining of the first wafer; and

e) thinning the first wafer until the pedestal is reached and attacked, wherein the thinning comprises fracturing the fragile zone of the first wafer,

wherein bonding energy between the first wafer and the second wafer is taken into account to obtain a determined width of the trimming of the chamfered edge region of the first wafer.

2. The method for assembly of two wafers according to claim 1 , wherein the etching is a chemical etching and the second wafer has a greater resistance to the chemical etching than the first wafer.

3. The method for assembly of two wafers according to claim 2 , wherein the etching is a chemical etching, and a surface of the second wafer is made of a different material from that of a surface of the first wafer and that permits selective chemical etching of the first wafer with respect to the second wafer.

4. The method for assembly of two wafers according to claim 1 , wherein the etching is a chemical etching, and the second wafer includes a layer of at least one material of SiO 2 or Si 3 N 4 , forming a stoppage means of stopping the chemical etching.

5. The method for assembly of two wafers according to claim 1 ,

wherein the first wafer is bonded onto the second wafer by a molecular adhesion technique.

6. The method for assembly of two wafers according to claim 1 , wherein the first wafer is bonded onto the second wafer by a layer of glue.

7. The method for assembly of two wafers according to claim 6 , wherein the etching is a chemical etching and the layer of glue acts as a means of stopping the chemical etching.

8. The method for assembly of two wafers according to claim 1 , wherein the pedestal is formed by chemical etching, the first wafer includes a protective layer against the chemical etching for forming the pedestal, and the method further comprises, prior to the chemical etching for forming the pedestal, chemical etching for eliminating a part of the protective layer located at a level of the pedestal.

9. The method for assembly of two wafers according to claim 8 , wherein the second wafer also includes a protective layer against the chemical etching for forming the pedestal, the chemical etching to eliminate the protective layer of the first wafer also eliminates the part of the protective layer of the second wafer that is located at a level of the pedestal to create an extension of the pedestal in the second wafer.

Assignments (2)
CHANGE OF NAME Recorded May 6, 2013
From: COMMISSARIAT A L'ENERGIE ATOMIQUE
To: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Reel/Frame 030352/0055 →
CHANGE OF NAME Recorded Feb 8, 2013
From: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 029779/0440 →
Priority Claims (1)
FR 04 13979 · Dec 28, 2004 · national
Continuity (2)
Division 11722115
Related Publication 20130078785A1 · Mar 28, 2013