Methods for forming narrow vertical pillars and integrated circuit devices having the same
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.
1. A method of forming an integrated circuit, comprising:
forming a first level mandrel on a first level over a substrate;
forming a first set of spacers extending in a first lateral direction along sidewalls of the first level mandrel;
forming a first level filler material at sides of spacers of the first set of spacers, the first level filler material and the first level mandrels defining a first level spacer volume there between;
forming a second level mandrel on a second level above the first level mandrel and the first level spacer volume, the second level mandrel crossing a width of the first level mandrel;
forming a second set of spacers extending in a second lateral direction along sidewalls of the second level mandrel, wherein each of the first set of spacers crosses a plurality of the second set of spacers and each of the second set of spacers crosses a plurality of the first set of spacers;
forming a second level filler material at sides of spacers of the second set of spacers;
selectively removing the second set of spacers to expose portions of the first level spacer volume;
selectively removing the exposed material in the first level spacer volume to form openings on the first level;
filling the openings associated with the first level spacer volume; and
forming a top electrode on a third level over the second level, the electrode extending directly over one or more of the filled openings on the first level.
2. The method of claim 1 , wherein filling the openings comprises forming a phase change material in the openings.
3. The method of claim 2 , further comprising providing a bottom electrode underlying the first set of spacers, wherein the first set of spacers are formed of a conductor and electrically interconnect the phase change material in the openings to the bottom electrodes.
4. The method of claim 1 , wherein forming the first set or second set of spacers comprises:
blanket depositing a layer of spacer material on the first or the second level mandrel; and
subjecting the layer of spacer material to a directional etch to define the first or second set of spacers.
5. A method of forming an integrated circuit, comprising:
forming a first level mandrel on a first level over a substrate;
forming a first set of spacers along sidewalls of the first level mandrel;
forming a first level filler material at sides of spacers of the first set of spacers, the first level filler material and the first level mandrels defining a first level spacer volume there between;
forming a second level mandrel on a second level above the first level mandrel and the first level spacer volume, the second level mandrel crossing a width of the first level mandrel;
forming a second set of spacers along sidewalls of the second level mandrel;
forming a second level filler material at sides of spacers of the second set of spacers;
selectively removing the second set of spacers to expose portions of the first level spacer volume, wherein selectively removing the second set of spacers defines trenches between the second level mandrel and the second level filler material;
selectively removing the exposed material in the first level spacer volume to form openings on the first level;
filling the openings, filling comprising forming a phase change material in the openings, wherein filling the openings also fills the trenches with phase change material; and
forming a top electrode on a third level over the second level, the electrode extending directly over one or more of the filled openings on the first level.
6. The method of claim 5 , further comprising:
removing the phase change material outside of the openings before forming the top electrode.
7. The method of claim 5 , wherein the top electrode electrically contacts the phase change material filling the trenches and phase change material forms a part of a phase change memory cell.
8. A method of forming an integrated circuit, comprising:
forming a first level mandrel on a first level over a substrate;
forming a first set of spacers along sidewalls of the first level mandrel;
forming a first level filler material at sides of spacers of the first set of spacers, the first level filler material and the first level mandrels defining a first level spacer volume there between;
recessing spacers of the first set of spacers after forming the first level filler material, thereby defining trenches in the first level spacer volume;
forming a dielectric material in the trenches;
after recessing the spacers of the first set of spacers and forming the dielectric material in the trenches, forming a second level mandrel on a second level above the first level mandrel and the first level spacer volume, the second level mandrel crossing a width of the first level mandrel;
forming a second set of spacers along sidewalls of the second level mandrel;
forming a second level filler material at sides of spacers of the second set of spacers;
selectively removing the second set of spacers to expose portions of the first level spacer volume;
selectively removing the exposed material in the first level spacer volume to form openings on the first level, wherein selectively removing the exposed material removes portions of the dielectric material;
filling the openings; and
forming a top electrode on a third level over the second level, the electrode extending directly over one or more of the filled openings on the first level.
9. A method for forming an integrated circuit, comprising:
providing a first set of spaced-apart lines of sacrificial material formed at a first vertical level and laterally separated by a first dielectric material;
providing a second set of spaced-apart lines of sacrificial material formed at a second vertical level above the first vertical level and laterally separated by a second dielectric material formed above the first dielectric material, each of the first set of spaced-apart lines crossing a plurality of the second set of spaced-apart lines, and each of the second set of spaced-apart lines crossing and contacting tops of a plurality of the first set of spaced-apart lines;
selectively removing the second set of spaced-apart lines and portions of the first set of spaced-apart lines at an intersection of the first and second sets of spaced-apart lines to form a spacer volume at the intersection of the first and second sets of spaced-apart lines; and
forming an electrode over a remainder of the first set of spaced-apart lines.
10. The method of claim 9 , wherein the integrated circuit is a phase change memory and wherein selectively removing the second set of spaced-apart lines and the portions of the first set of spaced-apart lines defines openings at the intersection of the first and second sets of spaced-apart lines, further comprising:
filling the openings with a phase change material.
11. The method of claim 10 , further comprising, after filling the openings, etching material around the openings to define free-standing memory cell stacks separated by open space, wherein each stack comprises an opening filled with the phase change material.
12. The method of claim 11 , further comprising depositing a third dielectric material in the space separating the free-standing memory cell stacks.
13. The method of claim 12 , wherein the third dielectric material in the space separating the free-standing memory cell stacks is different from the first dielectric material separating the first set of spaced-apart lines of sacrificial material.
14. The method of claim 12 , wherein the third dielectric material comprises the same dielectric material as one or both of the first and second dielectric materials.
15. The method of claim 9 , wherein the first and second dielectric materials comprise the same dielectric material.
16. The method of claim 9 , wherein the first and second dielectric materials comprise different dielectric materials.