IP Library Granted Patent US 8,847,227
Granted Patent B2
US 8,847,227 · App. 13/684,249 · Granted Sep 30, 2014

Display panel circuit structure

Inventors: Po-Hsin Lin (Hsinchu, TW); Chi-Liang Wu (Hsinchu, TW); Chin-Wen Lin (Hsinchu, TW); Ted-Hong Shinn (Hsinchu, TW)
Assignee: E Ink Holdings Inc.
H01L29/78G02F1/136259G02F2001/136263
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Quick Facts
Patent No.
US 8,847,227
App. No.
13/684,249
Granted
Sep 30, 2014
Kind
B2
Abstract

A display panel circuit structure includes a substrate, a first metal layer, a second metal layer, and a third metal layer. The first metal layer is disposed on the substrate. The second metal layer is disposed on the first metal layer and electrically connected to the first metal layer, in which the second metal layer has a pad area and a trace area connected to the pad area. The line width of the second metal layer in the pad area is greater than the line width of the second metal layer in the trace area. The third metal layer is disposed on the second metal layer, in which the third metal layer does not overlap the second metal layer n the trace area.

Claims (17)

1. A display panel circuit structure, comprising:

a substrate;

a first metal layer disposed on the substrate;

second metal layer disposed on the first metal layer and electrically connected to the first metal layer, wherein the second metal layer has a first pad, a second pad and a trace portion interconnected between the first pad and the second pad, and line widths of the first pad and second pad are greater than a line width of the trace portion; and

a third metal layer disposed on the second metal layer, wherein the third metal layer extends from a first position overlapped with the first pad to a second position overlapped with the second pad and the third metal layer is not overlapped with the trace portion of the second metal layer.

2. The display panel circuit structure as claimed in claim 1 , wherein the third layer is electrically connected to the first pad and the second pad respectively at the first position and the second position when the second metal layer is in a situation unable to conduct current.

3. The display panel circuit structure as claimed in claim 2 , wherein the first pad and the second pad are electrically connected to the third metal layer through laser welding.

4. The display panel circuit structure as claimed in claim 2 , wherein the first metal layer, the second metal layer, and the third metal layer in the first pad and the second pad are connected together through welding when the second metal layer is in the situation unable to conduct current.

5. The display panel circuit structure as claimed in claim 1 , wherein the second metal layer further comprises a bended area connected to the trace portion for altering extended direction, and a line width of the bended area is greater than the line width of the trace portion.

6. The display panel circuit structure as claimed in claim 1 , further comprising:

a first insulating layer disposed between the first metal layer and the second metal layer for partially separating the first metal layer and the second metal layer; and

a second insulating layer disposed between the second metal layer and the third metal layer for partially separating the second metal layer and the third metal layer.

7. The display panel circuit structure as claimed in claim 1 , wherein the first metal layer, the second metal layer, and the third metal layer are low-impedance conductive layers.

8. The display panel circuit structure as claimed in claim 1 , wherein the third metal layer is floating when the second metal layer is in a situation able to conduct current.

9. The display panel circuit structure as claimed in claim 1 , wherein the first metal layer is a gate layer of a transistor.

10. The display panel circuit structure as claimed in claim 1 , wherein the first metal layer comprises a third portion and a fourth portion spaced apart from the third portion, the third portion and the fourth portion being connected to and overlapped with the first pad and the second pad respectively,

wherein when the second metal layer is in a situation unable to conduct current, the third portion is electrically connected to the fourth portion through third metal layer, and the first pad and the second pad are connected with the third metal layer through welding.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2026
From: E INK HOLDINGS INC.
To: TRANSCEND OPTRONICS (YANGZHOU) CO., LTD
Reel/Frame 073680/0182 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2012
From: LIN, PO-HSIN; WU, CHI-LIANG; LIN, CHIN-WEN; SHINN, TED-HONG
To: E INK HOLDINGS INC.
Reel/Frame 029344/0435 →
Priority Claims (1)
TW 101103541 A · Feb 3, 2012 · national
Continuity (1)
Related Publication 20130200381A1 · Aug 8, 2013